Abstract: Disclosed is a method for enhanced efficiency and effectiveness in achieving timing closure of large, complex, high-performance digital integrated circuits. Circuit macros are re-optimized and re-tuned in the timing closure loop by means of a reformulated objective function that allows the optimizer to improve the slack of all signals rather than just the most critical one(s). The incentive to improve the timing of a sub-critical signal is a diminishing function of the criticality of the signal. Thus all signals are improved during the optimization, with the highest incentive to improve on the most critical signals, leading to faster and more effective overall timing closure.

Abstract: A method for identifying, in a VLSI chip design, circuits placed in an region of wiring congestion which can be replaced such that wiring tracks are freed up due to decreased net lengths without any pin to pin segment increasing in length. Circuits placed within the region of wiring congestion are identified and examined to determine the circuits they connect to. The placements of the connected circuits are analyzed to derive a rectangle of connectivity. Each of the originally identified circuits are then checked to determine if they are placed within their associated rectangle of connectivity. If not, the distance between the circuit and rectangle is calculated along with a recommended placement location, both of which are reported along with the circuit. The recommended placement location is a point along the border of the rectangle such that replacement of the circuit at the location reduces all circuit net lengths without increasing any pin to pin segment.

Abstract: According to an aspect of the invention, an electronic motor brake is provided which includes a braking circuit including one or more discharge devices connectable to one or more of a plurality of power supply lines carrying respective phases of a power supply for driving a direct current (DC) motor. Such electronic motor brake further includes an activation circuit driven by current returning from the motor through one or more of the power supply lines. The activation circuit is operable upon disconnecting the braking circuit from the plurality of the power supply lines to activate the discharge devices of the braking circuit to brake the motor.

Abstract: The present invention relates to data processing systems with built-in error recovery from a given checkpoint. In order to checkpoint more than one instruction per cycle it is proposed to collect updates of a predetermined maximum number of register contents performed by a respective plurality of CISC/RISC instructions in a buffer (CSB)(60) for checkpoint states, whereby a checkpoint state comprises as many buffer slots as registers can be updated by said plurality of CISC instructions and an entry for a Program Counter value associated with the youngest external instruction of said plurality, and to update an Architected Register Array (ARA)(64) with freshly collected register data after determining that no error was detected in the register data after completion of said youngest external instruction of said plurality of external instructions.

Abstract: Flat pseudo random test patterns are provided in combination with weighted pseudo random test patterns so that the weight applied to every latch in a LSSD shift register (SR) chain can be changed on every cycle. This enables integration of on-chip weighted pattern generation with either internal or external weight set selection. WRP patterns are generated by a tester either externally or internally to a device under test (DUT) and loaded via the shift register inputs (SRIs or WPIs) into the chip's shift register latches (SRLs). A test (or LSSD tester loop sequence) includes loading the SRLs in the SR chains with a WRP, pulsing the appropriate clocks, and unloading the responses captured in the SRLs into the multiple input signature register (MISR). Each test can then be applied multiple times for each weight set, with the weight-set assigning a weight factor or probability to each SRL.

Abstract: A high-performance gate library is augmented with tapered gates. The widths of the stacked devices are varied to reduce the delay through some of the input pins. For example in a tapered NAND gate the bottom devices in the NFET stack are have longer widths than the top device to achieve smaller top input to output pin delay at the expense of larger bottom input to output pin delay. The method of using synthesis algorithms modifies the input net to gate pin connections and swaps traditional non-tapered gates with tapered gates to improve the delay of the timing critical paths. The latest arriving gate input net is swapped with the net connected to the top pin. The gate is then converted to a tapered gate provided the paths through the bottom gate input(s) that are not timing critical.

Abstract: A method and system for I/O adapters that must rely on a central processor to handle all inbound link events to reduce the number of events signaled to the central processor with hardware state machines that sort out the significant link events and automatically generate the appropriate response on the outbound link thereby greatly reducing the central processor utilization. As optical links fail (unplugging the link is a failure) or when receiving multiple continuous sequences, numerous events must be filtered by the hardware state machines to limit the number of interrupts presented to the central processor.

Abstract: A SRAM sense amplifier timing circuit provides various delay settings for the sense amplifier enable signal (sae) and the sense amplifier reset signal (rse) in order to allow critical timing adjustments to be made for early mode, late mode conditions by varying the timing or with of the sense amplifier output pulse. These timing adjustments are programmable using scan in bits.

Abstract: A Land Grid Array structure is enhanced with a flex film interposer that not only provides a Land Grid Array (LGA) electrical connection between a Multi-Chip Module (MCM) and the next level of integration such as a system board, but also provides a reliable means to implement desired Engineering Change (EC) capability as well as a means for decoupling power to ground structure to minimize switching activity effects on the System. The invention as described can be implemented for EC repair, for Capacitive Decoupling or both.

Abstract: A method of calibrating an elastic interface is provided to automatically achieve a minimal cycle delay through the interface. An existing self-alignment interface (i.e. elastic interface) is used to de-skew within a cycle and stage the data to have it arrive on a given, programmed target cycle. However, this target cycle must be calculated in advance and may be larger than it needs to be, causing more latency on the interface. This method is used to determine the earliest target cycle (with or without additional guard-band). This target cycle is used to adjust the interface automatically to achieve this earliest target cycle. The determination of earliest target cycle can be done once, continuously, or using a sample window. The method also can be used for interfaces that have frequency multipliers or phase shifts at its boundaries.

Abstract: A method and device for parameter independent buffer underrun prevention in a data communication system includes a buffer for compensating for a difference in the rate of flow of data having a write port and a read port. After a commencement of writing data into the buffer, a predetermined delay time occurs. When the delay time has passed, reading data out from the buffer starts. Then the length of a time gap between the completion of writing data into the buffer and completion of reading data out from the buffer is determined. Finally, the length of the predetermined delay time is decreased by a first value if the length of the time gap is larger than a specified tolerance value and the length of the predetermined delay time is increased by a second value if the length of the time gap is smaller than the specified tolerance value. The provided method and device advantageously adjusts to systems having dynamically varying parameters, e.g.

Abstract: A method for allowing a partial instruction to be executed in a fixed point unit pipeline during the instruction dispatch cycle creates a mask used to select which bits of the operands participate in a future logical operation of the fixed point unit back a cycle to the instruction dispatch stage of the fixed point unit. As an S/390 System improvement applicable to other computers, the mask is determined and created two cycles ahead of execution, or two cycles before the mask is actually used. Also, in the method used for moving the mask generation back by one cycle, mask generation overlaps the dispatch stage in the I-unit, and this provides a handshake between the I-unit and E-unit of the fixed point unit of the central processor unit of the computer system. The control setting selection process occurs in a predetermination cycle stage or e-1 (em1) stage for the mask generation and the register file read address.

Abstract: A microprocessor and method for branch prediction selection provides the capability to select among multiple direction based history arrays for a single branch. A global selection counter when used in conjunction with a Prediction Method Comparison Table (PMCT) allows for branch direction accuracy to be improved on cold starts and context switches while maintaining high accuracy on long running code while minimizing silicon area and reducing power requirements.

Abstract: A method of calibrating an interface is provided to automatically achieve a minimal cycle latency while maintaining synchronous data arrival between a multiplicity of self-aligning interfaces. Independent self-alignment interfaces may de-skew data bits and have them arrive on a minimum cycle boundary. However, if all the interfaces do not arrive on the same cycle, SMP designs may not function properly. For instance, with a single control chip and multiple data chips on an AMP node, the control chip often sends out controls to the dataflow chips. If the data arriving on the elastic interfaces is not synchronized with the controls, the data is not routed properly. The method employs a calibration pattern to determine the latest cycle that data is received across the elastic interfaces and calculates the target cycle for all the interfaces to match this latest cycle.

Abstract: A device and method for storing information including an array of memory cells organized in bitlines and wordlines. The bitlines are subdivided in sections of wordlines and the sectioned bitlines are connected to a global bitline by a connector. The connector is made bidirectional and uses the high order part of the wordline addresses for this section of bitlines as a disable reset command. The reset stays active for unselected portions, compensating leakage of a mass of unselected cells which could disturb valid read signals.

Abstract: The invention relates to a technology of workload balancing for improved availability within a multitude of applications-servers and a multitude of application-clients interconnected with said application-servers by a communication network. A proposed method comprises a first-step, wherein an application-client is caching availability data of a subset of currently active application-servers as potential target application-servers. The method comprises a second-step, wherein for execution of an application-request the application-client selects an application-server from the subset based on a load-balancing decision of the application-client as target application-server. Finally the application-request is sent to the target application-server.

Abstract: An SMP computer system has an apparatus and method for recalibrating a self-timed, source-synchronous, pipelined interface while the computer system is running. The apparatus allows for quiescing the interface (ie. idling the processors to allow for no data transfers), raising fences (blocking interfaces), allowing for a quick clock centering recalibration step, and then unfencing and unquiescing to allow for the use of the interface again. The recalibration allows for compensating for drift over time on the interface to compensate for temperature, voltage, cycle time, and end-of-life degradation without bringing down and restarting the system.

Abstract: A digital camera supplies images to a first computer of a network via a receiver which is enabled as a bridge for Bluetooth, wireless LAN and infrared transmission from a digital camera. Once a digital camera is registered in a computer system, transmissions from the camera can be transmitted to the receiving first computer and thereafter transferred over the network for creation of a multi-media file which can be viewed at a private network or Internet accessible second computer.

Abstract: A method and computer system synchronize timing registers located throughout the computer system so that trace data from various sources in the system can be coordinated in time. This invention solves the problem when the multiple time stamp registers are loosely synchronized by relatively slow common timing pulses, but the phase relationship of the multiple time stamps to the common timing pulses is unknown to the firmware. By adding hardware to measure this phase relationship, the firmware can access this phase information to coordinate the time stamp information.

Abstract: Disclosed is a method and a computer circuit design for a dynamic clock ratio detector. The detector is used to determine the ratio between two clock domains. The detector has a driver 101 and a receiver, which reside in different clock domains. The driver 101 constantly produces a ratio clock pulse to the receiver. The ratio-counter in the receiver counts the pulse width based on its local clock cycles. The clock ratio detector has many features, including absorbing the meta-stability effect when the pulse crosses an asynchronous interface. The clock ratio detector prevents output counts oscillation, provides an adjustable ratio-detecting coverage range, a programmable system-parameter generator 104, and a programmable error reporter 105.