Patents Represented by Attorney, Agent or Law Firm Marian Underweiser
  • Patent number: 6577365
    Abstract: Disclosed is a method for forming an alignment layer for use in a liquid crystal display cell. The present invention includes a method of determining ion beam source operation parameters to provide a twist angle that is less than a predetermined maximum twist angle. The present invention also discloses a method for forming an improved liquid crystal display cell and an improved liquid crystal display.
    Type: Grant
    Filed: April 14, 2000
    Date of Patent: June 10, 2003
    Assignee: International Business Machines Corporation
    Inventors: Praveen A. Chaudhari, Eileen Ann Galligan, James Patrick Doyle, James Andrew Lacey, Shui-Chih Alan Lien, Hiro Nakano
  • Patent number: 6566210
    Abstract: The present invention provides a method of preparing a Si-based metal-insulator-semiconductor (MIS) transistor which prevents the polycrystalline grains of the gate conductor from getting significantly larger by reducing the thermal budget of the sidewall oxidation process. The thermal budget of the inventive sidewall oxidation process is reduced one or two orders of magnitude over conventional prior art sidewall oxidation processes by utilizing atomic oxygen as the oxidizing ambient. The present invention also provides Si-based MIS transistors having a gate conductor having grain sizes of about 0.1, preferably 0.05, &mgr;m or less.
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: May 20, 2003
    Assignee: International Business Machines Corporation
    Inventors: Atul C. Ajmera, Omer H. Dokumaci, Bruce B. Doris, Oleg Gluschenkov
  • Patent number: 6556271
    Abstract: A method of manufacturing a color liquid crystal display element. The method includes the steps of: forming coloring layers composed of a plurality of colors on a transparent substrate on which a thin film transistor structure, a gate line and a data line are formed; forming a transparent conductive film over the entire transparent substrate on which the coloring layers are formed; coating the entire surface of the transparent conductive film with a negative resist; exposing the negative resist to a light using the gate line and the data line as a photomask, the light being emitted from a light source facing a back side of the transparent substrate, the light substantially having wavelength bands excluding 390 nm to 440 nm; developing and baking the exposed negative resist; and etching and removing the transparent conductive film in a portion where the negative resist is removed.
    Type: Grant
    Filed: May 15, 2000
    Date of Patent: April 29, 2003
    Assignee: International Business Machines Corp.
    Inventors: Takatoshi Tsujimura, Taro Hasumi
  • Patent number: 6538709
    Abstract: A liquid crystal display panel part group composed of a plurality of panel parts such as an array cell, a optical system sheet family, a light guide plate, a lamp reflector, and a lamp, and a liquid crystal display panel is enveloped in a film for laminating the parts. This film may be provided so as to cover the whole of the liquid crystal display panel part group and the film may have an opening. In order to adjust the positions of the parts, convex and concave portions are provided in the liquid crystal display panel parts.
    Type: Grant
    Filed: December 15, 1998
    Date of Patent: March 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: Mikio Kurihara, Yasuhiro Kimura
  • Patent number: 6538919
    Abstract: The use of ferrimagnetic materials is proposed for use in magnetic devices. Such magnetic devices include magnetic tunnel junctions (MTJ) which have at least two magnetic layers separated by an insulating barrier layer, wherein at least one of the two magnetic layers is ferrimagnetic. Such MTJ's are used in MRAM (magnetic random access memory) structures. Where the magnetic device is a magnetic sensor, it preferably includes a layer that comprises a ferrimagnetic material separated from another magnetic layer by a barrier layer and the magnetizations of the magnetic layer are oriented at an angle to one another.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: March 25, 2003
    Assignee: International Business Machines Corporation
    Inventors: David W. Abraham, Stuart S. P. Parkin, John C. Slonczewski, Philip L. Trouilloud
  • Patent number: 6529189
    Abstract: The invention is embodied in a wireless stylus that incorporates, for example, an infrared emitter for communicating with a receiver associated with a computer. The stylus is provided with push-buttons near its tip that can be actuated by the user during the course of pointing the stylus at a touch screen location. Accordingly, by the combined actuation of the touch screen and a concurrent actuation of one or more of the push buttons, a mouse input to the computer is accomplished.
    Type: Grant
    Filed: February 8, 2000
    Date of Patent: March 4, 2003
    Assignee: International Business Machines Corporation
    Inventors: Evan George Colgan, James Lewis Levine, Michael Alan Schappert
  • Patent number: 6518827
    Abstract: A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: February 11, 2003
    Assignee: International Business Machines Corporation
    Inventors: John A. Fifield, Robert H. Dennard, Russell J. Houghton, Toshiaki Kirihara, Wing Luk
  • Patent number: 6509947
    Abstract: A device and method for maintaining the volume of a liquid contained within a cavity between two substrates to something equal or nearly equal to that of the volume of the cavity. A particular application is a liquid crystal display (LCD), in which a liquid crystal (LC) material is contained within a cavity between two flat display substrates. The device serves to minimize the volume differential between the liquid and the cavity caused by a change in temperature of the display, such that the formation of bubbles within the liquid is substantially or completely prevented. In so doing, the device essentially eliminates thermally-induced defects that would otherwise be visible to the user.
    Type: Grant
    Filed: December 19, 2000
    Date of Patent: January 21, 2003
    Assignee: International Business Machines Corporation
    Inventors: Robert Jacob von Gutfeld, James Henry Glownia, Richard Allen John, Shui-Chih Alan Lien
  • Patent number: 6503664
    Abstract: The fabrication of transmissive attenuating types of phase shift masks by formation of and selective etch of a layer, deposited on a substrate. This single layer provides both the phase shift and the attenuation required and is readily patterned and processed to produce attenuating phase shift masks.
    Type: Grant
    Filed: April 9, 1999
    Date of Patent: January 7, 2003
    Assignee: International Business Machines Corporation
    Inventors: Derek Brian Dove, Kwang Kuo Shih
  • Patent number: 6501217
    Abstract: An organic light emitting device is provided which includes a cathode (51), an anode (47, 46, 48), and an organic electroluminescent region (49, 50). The anode includes a metal layer (46), a barrier layer (47), and an anode modification layer (48). Light is emitted through the cathode (51) when a voltage is applied between the anode (47, 46, 48) and the cathode (51).
    Type: Grant
    Filed: January 10, 2000
    Date of Patent: December 31, 2002
    Assignee: International Business Machines Corporation
    Inventors: Tilman A. Beierlein, Eliav Haskal, Heike Riel, Walter Riess, Paul Seidler, Samuel Clagett Strite, Horst Vestweber
  • Patent number: 6490217
    Abstract: A magnetic memory device for selectively writing one or more memory cells in the memory device includes a plurality of global write lines for selectively conveying a destabilizing current, the global write lines being disposed from the memory cells such that the destabilizing current passing through the global write lines does not destabilize unselected memory cells in the memory device, each global write line including a plurality of segmented write lines operatively connected thereto. The memory device further includes a plurality of segmented groups, each segmented group including a plurality of memory cells operatively coupled to a corresponding segmented write line, each segmented write line being disposed in relation to the plurality of corresponding memory cells such that the destabilizing current passing through the segmented write line destabilizes the corresponding memory cells for writing.
    Type: Grant
    Filed: May 23, 2001
    Date of Patent: December 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: John Kenneth DeBrosse, William Robert Reohr
  • Patent number: 6472804
    Abstract: An electrode for an electro-optical device is provided. Light is passing through this electrode which comprises a pattern of conductive elements. The elements have dimensions small compared to the wavelength of light, so that the electrode appear transparent. The light intensity distribution after having penetrated the electrode compared with the light intensity distribution before having penetrated the electrode is influenced by forward scattering.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: October 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: Peter Mueller, Walter Riess
  • Patent number: 6472705
    Abstract: The present invention is directed to a microelectric device and especially a Field effect transistor comprising a source, drain, channel, an insulating layer overlying said channel containing at least one closed cage molecule, said closed cage molecule being capable of exhibiting a Coulomb blockade effect upon application of a voltage between said source and drain. Two different microelectronic devices are described containing the closed cage molecule, a logic cell and a memory cell.
    Type: Grant
    Filed: November 18, 1998
    Date of Patent: October 29, 2002
    Assignee: International Business Machines Corporation
    Inventors: Donald Stimson Bethune, Sandip Tiwari
  • Patent number: 6452649
    Abstract: In a flat surface illumination device or a liquid crystal display panel, with an aperture disposed in a frame or a case, comprising a circumferential section in which a central section receiving and supporting the light guide and the like is removed, a warp preventing means is formed in such a manner to cross the aperture. The warp preventing means comprises a long and narrow zonal thin plate in which two or more beading processes are performed.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Masaki Ono, Mikio Suzuki, Masanori Mori
  • Patent number: 6452240
    Abstract: In order to dampen magnetization changes in magnetic devices, such as tunnel junctions (MTJ) used in high speed Magnetic Random Access Memory (MRAM), a transition metal selected from the 4d transition metals and 5d transition metals is alloyed into the magnetic layer to be dampened. In a preferred form, a magnetic permalloy layer is alloyed with osmium (Os) in an atomic concentration of between 4% and 15% of the alloy.
    Type: Grant
    Filed: October 30, 2000
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corporation
    Inventors: Snorri T. Ingvarsson, Roger H. Koch, Stuart S. Parkin, Gang Xiao
  • Patent number: 6448131
    Abstract: A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.
    Type: Grant
    Filed: August 14, 2001
    Date of Patent: September 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Cyril Cabral, Jr., Kevin K. Chan, Guy M. Cohen, Ramachandra Divakaruni, Christian Lavoie, Fenton R. McFeely
  • Patent number: 6448173
    Abstract: A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.
    Type: Grant
    Filed: June 7, 2000
    Date of Patent: September 10, 2002
    Assignee: International Business Machines Corporation
    Inventors: Lawrence Alfred Clevenger, Ronald Gene Filippi, Kenneth Parker Rodbell, Roy Charles Iggulden, Chao-Kun Hu, Lynne Marie Gignac, Stefan Weber, Jeffrey Peter Gambino, Rainer Florian Schnabel
  • Patent number: 6440560
    Abstract: The present invention relates to a novel organosilicon particle having the formula SiaObCcHd. The particle may be coated with an organic film, preferably a rigid connector compound. The present invention also provides a method of using the organosilicon particle and/or rigid connector compound in the formation of a low-k dielectric film.
    Type: Grant
    Filed: July 26, 1999
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corporation
    Inventors: Stephen McConnell Gates, Christopher Bruce Murray
  • Patent number: 6437422
    Abstract: Active devices that have either a thread or a ribbon geometry. The thread geometry includes single thread active devices and multiple thread devices. Single thread devices have a central core that may contain different materials depending upon whether the active device is responsive to electrical, light, mechanical, heat, or chemical energy. Single thread active devices include FETs, electro-optical devices, stress transducers, and the like. The active devices include a semiconductor body that for the single thread devices is a layer about the core of the thread. For the multiple thread devices, the semiconductor body is either a layer on one or more of the threads or an elongated body disposed between two of the threads. For example, a FET is formed of three threads, one of which carries a gate insulator layer and a semiconductor layer and the other two of which are electrically conductive and serve as the source and drain. The substrates or threads are preferably flexible and can be formed in a fabric.
    Type: Grant
    Filed: May 9, 2001
    Date of Patent: August 20, 2002
    Assignee: International Business Machines Corporation
    Inventors: Paul M. Solomon, Jane Margaret Shaw, Cherie R. Kagan, Christos Dimitrios Dimitrakopoulos, Tak Hung Ning
  • Patent number: 6437596
    Abstract: An improved apparatus for testing an array of pixel cells formed on a substrate is provided. Each pixel cell is coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines formed on the substrate. The gate lines and/or data lines are partitioned into a plurality of groups. For each particular group, a first probe pad and select logic is formed on said substrate. The select logic, which is coupled between the first probe pad and the lines of the particular group, selectively couples the first probe pad to the lines of said particular group based upon first control signals supplied to the select logic during a test routine whereby charge is written to, stored, and read from the array of pixel cells. In addition, a second probe pad and hold logic for each particular group may be formed on the substrate.
    Type: Grant
    Filed: January 28, 1999
    Date of Patent: August 20, 2002
    Assignee: International Business Machines Corporation
    Inventors: Leslie Charles Jenkins, Frank Robert Libsch, Michael Patrick Mastro, Robert Wayne Nywening, Robert John Polastre