Abstract: In a flat surface illumination device or a liquid crystal display panel, with an aperture disposed in a frame or a case, comprising a circumferential section in which a central section receiving and supporting the light guide and the like is removed, a warp preventing means is formed in such a manner to cross the aperture. The warp preventing means comprises a long and narrow zonal thin plate in which two or more beading processes are performed.

Abstract: In order to dampen magnetization changes in magnetic devices, such as tunnel junctions (MTJ) used in high speed Magnetic Random Access Memory (MRAM), a transition metal selected from the 4d transition metals and 5d transition metals is alloyed into the magnetic layer to be dampened. In a preferred form, a magnetic permalloy layer is alloyed with osmium (Os) in an atomic concentration of between 4% and 15% of the alloy.

Abstract: A method and structure for preventing damage to an electronic device. The structure includes a sensor outputting signals indicating environmental conditions experienced by the electronic device, a non-volatile memory storing ones of the signals that exceed a limit, and an output device outputting signals stored in the non-volatile memory, thereby providing a history of the environmental conditions experienced by the electronic device that exceed the limit.

Abstract: A dual damascene process capable of reliably producing aluminum interconnects that exhibit improved electromigration characteristics over aluminum interconnects produced by conventional RIE techniques. In particular, the dual damascene process relies on a PVD-Ti/CVD-TiN barrier layer to produce aluminum lines that exhibit significantly reduced saturation resistance levels and/or suppressed electromigration, particularly in lines longer than 100 micrometers. The electromigration lifetime of the dual damascene aluminum line is strongly dependent on the materials and material fill process conditions. Significantly, deviations in materials and processing can result in electromigration lifetimes inferior to that achieved with aluminum RIE interconnects. In one example, current densities as high as 2.5 MA/cm2 are necessary to induce a statistically relevant number of fails due to electromigration.

Abstract: A method for increasing the trench capacitor surface area is provided. The method, which utilizes a metal silicide to roughen the trench walls, increases capacitance due to the increase in the trench surface area after the silicide has been removed. The roughening of the trench walls can be controlled by varying one or more of the following parameters: the density of the metal, the metal film thickness, the silicide phase, and the choice of the metal. Once the metal is deposited in the trench, the method is self-limited. Shrinking the trench to its original width can be obtained by subsequent silicon deposition or by diffusion of silicon from a cap layer through the silicide.

Abstract: A low cost LCD device employing a high speed field sequential drive scheme.

Abstract: A semiconductor memory and a method of producing the memory, includes a transistor including a first gate having an oxide, and a channel, and a back-plane including a second gate and an oxide thereover, the second gate formed opposite to the channel of the transistor, the second gate including a floating gate, wherein a thickness of the oxide of the back-plane is separately scalable from an oxide of the first gate of the transistor.

Abstract: The present invention relates to a novel organosilicon particle having the formula SiaObCcHd. The particle may be coated with an organic film, preferably a rigid connector compound. The present invention also provides a method of using the organosilicon particle and/or rigid connector compound in the formation of a low-k dielectric film.

Abstract: A method and structure for simultaneously producing a dynamic random access memory device and associated transistor is disclosed. The method forms channel regions and capacitor openings in a substrate. Next, the invention deposits capacitor conductors in the capacitor openings. Then, the invention simultaneously forms a single insulator layer above the channel region and above the capacitor conductor. This single insulator layer comprises a capacitor node dielectric above the capacitor conductor and comprises a gate dielectric above the channel region.

Abstract: Active devices that have either a thread or a ribbon geometry. The thread geometry includes single thread active devices and multiple thread devices. Single thread devices have a central core that may contain different materials depending upon whether the active device is responsive to electrical, light, mechanical, heat, or chemical energy. Single thread active devices include FETs, electro-optical devices, stress transducers, and the like. The active devices include a semiconductor body that for the single thread devices is a layer about the core of the thread. For the multiple thread devices, the semiconductor body is either a layer on one or more of the threads or an elongated body disposed between two of the threads. For example, a FET is formed of three threads, one of which carries a gate insulator layer and a semiconductor layer and the other two of which are electrically conductive and serve as the source and drain. The substrates or threads are preferably flexible and can be formed in a fabric.

Abstract: An improved apparatus for testing an array of pixel cells formed on a substrate is provided. Each pixel cell is coupled to at least one gate line of a plurality of gate lines formed on the substrate and at least one data line of a plurality of data lines formed on the substrate. The gate lines and/or data lines are partitioned into a plurality of groups. For each particular group, a first probe pad and select logic is formed on said substrate. The select logic, which is coupled between the first probe pad and the lines of the particular group, selectively couples the first probe pad to the lines of said particular group based upon first control signals supplied to the select logic during a test routine whereby charge is written to, stored, and read from the array of pixel cells. In addition, a second probe pad and hold logic for each particular group may be formed on the substrate.

Abstract: The present invention pertains to new flip-chip organic opto-electronic structures and methods for making the same. The new organic opto-electronic device includes at least two separate parts. Each part comprises an electrode and at least one of these electrodes carries an organic stack. After completion of these separate parts both are brought together to form the complete opto-electronic device. It is a crucial aspect of the new flip-chip approach that spacers are integrated on one or both sides of the parts and that an interface formation process is employed.

Abstract: An N-channel metal oxide semiconductor (NMOS) driver circuit (and method for making the same), includes a boost gate stack formed on a substrate and having a source and drain formed by a low concentration N-type implantation, and an N-driver coupled to the boost gate stack.

Abstract: An organic light emitting device (and a method for producing the device) includes a multilayered structure with a substrate layer providing a first electrode layer, a second electrode layer and at least one light emitting organic material layer between the first and second electrode layers. The second electrode layer includes at least two separate layers. That is, a semi-transparent metal electrode layer and a light transparent lateral conductor layer is deposited onto the light emitting organic material layer by depositing the semi-transparent metal electrode layer onto the light emitting organic material layer, depositing subsequently at least one protection layer thereupon and depositing the light transparent lateral conductor layer onto the protection layer.

Abstract: A bistable liquid crystal display cell comprises at least two compartments separated by thin transparent membranes. A first compartment contains a first liquid crystal mixture between a first substrate and a thin transparent membrane. A second compartment contains a second liquid crystal mixture between a second substrate and a thin transparent membrane. The mixtures have a first alignment in which they are both aligned parallel to the plane of the display cell, but orthogonal to each other, and a second alignment in which they are both aligned normal to the plane of the display cell. Each compartment has a grating located on a surface of the compartment.

Abstract: An organic light emitting device is provided having a substrate (60), an anode contact electrode (64), a cathode contact electrode (61), and an organic region (62, 63) in which electroluminescence takes place if a voltage is applied between the anode (64) and cathode (61). At least one of the electrodes (61, 64) comprises a non-degenerate wide bandgap semiconductor.

Abstract: A method for constructing oxide electrodes for use in an OxFET device is disclosed. The electrodes are formed by first depositing a double layer of conducting perovskite oxides onto an insulating oxide substrate. A resist pattern with the electrode configuration is then defined over the double layer by means of conventional lithography. The top oxide layer is ion milled to a depth preferably beyond the conducting oxide interface, but without reaching the substrate. Chemical etching or RIE is used to remove the part of the lower conductive oxide layer exposed by ion milling without damaging the substrate. Source and drain electrodes are thereby defined, which can be then be used as buried contacts for other perovskites that tend to react with metals. Also disclosed is a field effect transistor structure which includes these source and drain electrodes in a buried channel configuration.

Abstract: A static redundancy arrangement for a circuit using a focused ion beam anti-fuse methodology which reduces the circuit layout area and the switching activity compared to a prior art dynamic redundancy scheme, resulting in less power, a simpler design and higher speed. Focused ion beam anti-fuse methodology is used to program redundancy for circuits, particularly wide I/O embedded DRAM macros. An anti-fuse array circuit is comprised of a plurality of anti-fuse programming elements, each of which comprises a latch circuit controlled by a set input signal, and an anti-fuse device which is programmed by a focused ion beam.

Abstract: A method of generating or modifying patterns of topically specific magnetic modifications in an at least potentially ferromagnetic surface comprising the step of subjecting the surface to a controlled impact of energized subatomic particles, preferably in the form of electron radiation, directed at the surface for producing a predetermined pattern of discrete magnetized areas on the surface. The method serves to increase the density of magnetically coded information on magnetic media, such as hard disks.

Abstract: A field compensation circuit for selectively writing one or more selected magnetic memory cells in a magnetic random access memory (MRAM) includes a controller for detecting a characteristic representative of an anticipated interaction between a magnetic field emanating from a bit line corresponding to a selected memory cell and at least one stray magnetic field emanating from one or more bit lines associated with one or more memory cells in close relative proximity to the selected memory cell. A control signal generated by the controller is indicative of the detected characteristic. The field compensation circuit further includes a programmable current source operatively coupled to the bit line corresponding to the selected memory cell, the programmable current source including an input for receiving the control signal. The programmable current source generates a write current having a magnitude which varies in response to the control signal.