Abstract: A switch recovery circuit is disclosed for improving the efficiency of switching voltage regulators. The switch recovery circuit includes a first and second inductor, a capacitor, a first diode, and a recovery circuit. The capacitor and diode comprise an AC coupled loop circuit around the first inductor. Current flows through the loop circuit soon after the switch is opened and charges the capacitor. The recovery circuit, which includes a second inductor that is magnetically coupled to the first inductor, provides current, at least some of which discharges the capacitor (i.e. current that flows in the opposite direction to the loop current) after the loop current stops. A second diode is interposed in series with the second inductor to provide appropriate voltage offsets in the circuit and to prevent the first inductor from being shorted to ground through the second inductor.

Abstract: Circuits and methods for a delta-sigma analog-to-digital converter having a variable oversample ratio to produce a constant fullscale output at reduced circuit complexity, die area, and power dissipation are provided. The circuits and methods consist of scaling the digital input to the digital filter with a decoder whose size depends on the number of oversample ratios allowed by the analog-to-digital converter. The digital filter is implemented as a comb filter having a cascade of N integrators and N differentiators, where N is the order of the digital filter. The size of the differentiators is equal to the number of bits used as output for the analog-to-digital converter, which is smaller than the size of the integrators and the number of bits produced by the digital filter.

Abstract: Methods and apparatus for calibrating volume measurement in a plethysmographic chamber are described. The present invention involves the use of a calibration volume chamber of known volume coupled to a plethysmographic measurement chamber in a plethysmographic measurement system for determining body composition, wherein a computer system calibrates the measurement system prior to conducting a volume measurement of a test subject, by measuring the chamber volume before and after opening an electronically controlled valve that connects the controlled calibration volume to the plethysmographic chamber, and comparing the measured chamber volumes based on the known reference volume.

Abstract: Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.

Abstract: Circuits and methods for providing an accurate phase shift between a generated output signal and an input signal are disclosed. The circuits and methods enable any amount of accurate phase shift to be set without requiring significant changes in circuitry with each phase shift. The phase shift is set by a voltage applied to a feedback amplifier connected to a low-pass filter and a timer circuit that resets a latch circuit.

Abstract: Apparatus and methods relating to plethysmographic measurement of infant body composition are provided. A tray for receiving the infant subject to be measured is coupled to a sliding mechanism that slides the tray in and out of a plethysmographic measurement chamber, thereby reducing the footprint of said chamber and facilitating infant comfort during measurement. Further, an integrated weighing function is provided that determines the infant's weight while conducting body composition measurements.

Abstract: An electronic circuit to cancel the input bias currents of a differential amplifier over most of the common-mode input voltage range is provided. The circuit includes an arrangement of transistors, current mirror and current sources to track the input bias currents of the differential amplifier even when the common-mode voltage is within at least 0.2 volts of the supply rail voltage level. The input bias cancellation currents are generated by tracking the input bias currents and injected into the differential amplifier inputs to cancel the input bias currents. The circuit includes a bootstrap loop to track the input bias currents when the common-mode voltage fluctuates.

Abstract: A circuit and method for controlling a switching voltage regulator having (1) a switch including one or more switching transistors and (2) an output adapted to supply current at a regulated voltage to a load including an output capacitor. The circuit and method generates a control signal to turn said one or more switching transistors OFF under operating conditions when the voltage at the output is capable of being maintained substantially at the regulated voltage by the charge on the output capacitor. Such a circuit and method increases the efficiency of the regulator circuit particularly at low average current levels.

Abstract: Circuits and methods for extending the input common mode voltage range of a JFET op-amp are provided. The circuits and methods consist of modifying the input stage of a JFET op-amp to include a BJT pair as the input differential pair and use a JFET pair as followers. Using the BJTs as the input differential pair enables the JFET followers to operate in the linear region of operation when the op-amp's input is approaching ground, thereby increasing the negative common mode voltage range. The positive common mode voltage range is increased by reducing the source current in the JFET pair and using a transistor pair as clamping transistors.

Abstract: A voltage reference circuit capable of operating at reduced quiescent currents is described. The voltage reference circuit comprises an output circuit, a timer circuit and a control circuit. When in standby mode, in order to decrease power consumed by the output circuit, current through the output circuit is decreased, allowing the voltage at the output node to fall outside of a desired range. To determine when this event has occurred, the control circuit includes a test circuit that generates a test signal characterized by having a voltage that is correlated with the voltage at the output terminal.

Abstract: Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.

Abstract: Circuitry and methods are provided for reducing rise time associated with signals on an open-drain or open-collector signal line. Signal line voltage is monitored to determine if the signal line is being pulled LOW. If the signal line is not being pulled LOW, as indicated by signal line voltage exceeding a threshold level, additional pullup current is provided. The additional current may be provided gradually in relation to the signal line voltage, or may be provided in full whenever voltage exceeds the threshold. Circuitry may also be provided to monitor voltage slew rate on the signal line, and to enable the additional pullup current only when the slew rate exceeds a positive threshold level.

Abstract: A completely tunable second order low-pass filter with minimal active circuitry is disclosed. The filter provides a very flexible choice of filter parameters such as cutoff frequency, DC gain, and Q factor, by selecting appropriate resistor values for a single integrated circuit with much lower capacitance, capacitance ratio, and active circuitry than other standard low-pass circuit configurations.

Abstract: A circuit and method for controlling a switching voltage regulator having (1) a switch including one or more switching transistors and (2) an output adapted to supply current at a regulated voltage to a load including an output capacitor. The circuit and method generates a control signal to turn said one or more switching transistors OFF under operating conditions when the voltage at the output is capable of being maintained substantially at the regulated voltage by the charge on the output capacitor. Such a circuit and method increases the efficiency of the regulator circuit particularly at low average current levels.

Abstract: Methods and systems for rendering and displaying in a real time 3-D computer graphic system a sequence of images of a subject using a plurality of time-sequenced textures such that at least a portion of the subject appears animated. The time-sequenced textures are derived from sources such as digitized frames or fields captured from a video recording of a live actor who may be engaged in a scripted performance, or a digitally-recorded cartoon animation sequence, and can be mapped in different ways to different types of surface geometries to achieve animation.

Abstract: A network-type data processing system is provided. The system can support multiple simultaneous exchanges of data, and includes multi-port storage devices in which all ports can be active at all times. On initialization of the system, each storage device can announce itself through all of its ports simultaneously.

Abstract: Methods and systems are presented in which at least one geometric distortion function is separately determined for application to a particular primary color component of a color video display to cause a geometric distortion that compensates for lateral chromatic aberration in an optical system used to view the display.

Abstract: A driver circuit for driving top and bottom power transistors stacked between two supply terminals is provided. The driver circuit includes shoot-through reduction means for monitoring the gate-to-source voltages of the two power transistors so as to inhibit the turning-ON of each power transistor until the gate-to-source voltage of the other power transistor has fallen to a voltage level indicative of the other transistor being OFF. Additionally, the driver circuit which can utilize a bootstrap capacitor for providing enhanced voltages to drive the top power transistor, also includes a bootstrap capacitor recharge means to monitor the output voltage of the circuit so as to inhibit the turning-ON of the top power transistor until the bootstrap capacitor has had sufficient time to recharge.

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.

Abstract: A scheduling mechanism is provided for controlling when the arbitration circuit of a node sharing a CSMA communication medium is to start CSMA arbitration for access to the communication medium once the node has a message ready for transmission, the scheduling mechanism delaying the arbitration circuit from seeking access if total transmission activity on the communication medium exceeds a total use threshold value and transmission activity of the node exceeds a local use threshold value, and otherwise permitting the arbitration circuit to seek access to the communication medium by arbitration in accordance with a priority value assigned to the node.