Abstract: An apparatus and method for compressing pseudo-random data is provided. The apparatus and method make use of stochastic distribution models to generate approximations of the input data. A data sequence obtained from the stochastic distribution models is compared to the input data sequence to generate a difference data sequence. The difference data sequence tends to be less “random” than the input data sequence and is thus, a candidate for compression using pattern repetition. The difference data sequence is compressed using standard compression techniques and stored as a compressed data file along with information identifying the stochastic distribution model used and any parameters of the stochastic distribution model, including seed value and the like. When decompressing a data file compressed in the manner described above, the compressed difference data sequence is decompressed and a data sequence is generated using the identified stochastic distribution model and model parameters.

Abstract: A method for analyzing a design or a model of a microprocessor chip model is provided. A base chip model is generated, and it is modified with wire-only changes to produce a modified chip model. The modified chip model is compared to the base chip model to discern the wire-only changes to form a delta chip model. A set of values for RC delays and net capacitance based on the delta chip model is produced, and the modified chip model is timed using the set of values for RC delays and net capacitance on the delta chip model and RC delays and net capacitance on the base chip model.

Abstract: An alignment system has one or more paired tabs and slots. The tabs are located on one component and the slots are located in another component to provide alignment between the components in three dimensions even if the tabs and slots are beyond the view or not visible to the user. The tab is a flat protrusion having short side edges and tapered front edges that converge to a central tip. The slot is a large, generally diamond-shaped aperture with rectangular slits on two opposed corners. Initially, the tabs on the first component are misaligned in three dimensions relative to the slots in the second component. As the tips of the tabs move into the slots, the tips make contact with the diamond-shaped apertures. The large size and shape of the slots allow for a significant range of misalignment between the components. After initial capture, the tapered front edges of the tabs slide along the apertures to provide coarse deflection and centering.

Abstract: A method and system for an approximation of a filter function for computing a characteristic value of an output pixel based on characteristic values of a plurality of input pixels is provided. A filter response curve adjustment value is obtained, preferably from a lookup table, based on a distance interval between coordinates of the output pixel and coordinates of a selected input pixel. A normalized filter response curve input value is computed based on the distance interval and the filter response curve adjustment value, preferably by adding the values together. The characteristic values at a plurality of input pixels are obtained. A linearly interpolated value for the characteristic value of the output pixel is then computed based on the characteristic values of the plurality of input pixels and the normalized filter response curve input value.

Abstract: A method and apparatus in a data processing system for manipulating a set of binary decision diagrams. A plurality of segments is created from the set of binary decision diagrams. A group of compression codes is associated with the set of segments, wherein the group of compression codes form a compressed data structure representing the set of binary decision diagrams.

Abstract: A device for use with a computer drawer assembly, the computer drawer assembly including a safety latch. The device comprises a first planar portion and a second planar portion coupled to the first planar portion wherein the second planar portion retracts the safety latch during the slidable operation of the computer system. The device eliminates the tedious process of having to manually retract the safety latch with a screwdriver-type tool when using the computer drawer assembly. This adds significant convenience when a system operator needs to slidably maneuver the computer drawer assembly.

Abstract: A method and system for verifying a correct orientation of a module during installation of the module into a circuit board mounting site. The module housing is symmetric in at least one respect such that the module may be positioned in at least one alternate orientation with respect to the mounting site in addition to the correct orientation. Within the module, a module test contact is electrically connected to a common plane mode contact. A mounting site test contact that engages the module test pin when the module is correctly aligned with respect to the mounting site is preselected to be tested upon placement of the module onto the mounting site. A test signal is applied to a conductive common plane within the mounting site to which a common plane mounting site contact is connected. Prior to installation of the module into the mounting site, the mounting site test contact is electrically isolated from the conductive common plane to which a test signal is applied.

Abstract: A method of maintaining cache-coherency in a multi-processor computer system provides new states to indicate that a sector in an upstream cache has been modified, without executing unnecessary bus transactions for the lower-level cache(s). These new “U” states can indicate which sector in the cache line was modified, or if the cache line was the subject of a cachable write-through operation. The protocol is implemented as an improvement to the prior-art “MESI” cache-coherency protocol. The new protocol is especially useful in handling allocate-and-zero instructions wherein data is modified in the cache (zeroed out) without first fetching the old data from memory. In the embodiment wherein there are only two sectors in a given cache line, three new states are provided to indicate which sector was modified, or whether any cachable write-through operation was performed on the cache line of the first-level cache.

Abstract: A method of providing an interconnection between one or more peripheral devices and a system bus of a computer system selectively establishes and removes a connection from a primary peripheral bus to a secondary peripheral buses, and determines a target from among the one or more peripheral devices when a bus bridge is a master of the primary peripheral bus, using an address decoder. Access to and from the primary peripheral bus is controlled using an arbiter to select a master for the primary peripheral bus from among the one or more peripheral devices, to allow both (i) selective establishing and removing of a connection from the primary peripheral bus to one of the secondary peripheral buses in response to the selection of the master, and (ii) isolating of the master prior to establishing the connection to the secondary peripheral bus. Hot Plug Control Logic and Switch Control Logic in conjunction with the arbiter allows Hot Plug support along with the expanded slot environment.

Abstract: An automatic power docking mechanism for establishing a power connection between a computer electronic subsystem and a power distribution board within a computer chassis is provided. In one embodiment, the power docking mechanism includes power pads electrically coupled to a power distribution board and a housing with slotted openings secured over the power pads. The housing's slotted openings are configured to receive power bus bars from a computer subsystem and hold the bus bars in contact with the power pads.

Abstract: A method, system, and computer program product are disclosed for determining the address type of a serial EEPROM in an electronic system. The method includes reading data from at least one location of the EEPROM for a first time and saving the data for future reference. Thereafter, a sequence of transactions is executed that alters the contents of the EEPROM in a prescribed manner if the EEPROM is of a first type. The sequence of transaction leaves the EEPROM in an unaltered state if the EEPROM is of a second type. Data is then read from at least one location of the EEPROM for a second time. The location of the data read from the EEPROM the second time is the same as the location of the data read the first time if the EEPROM is of the first type. The data read the first time and the data read the second time are then compared.

Abstract: A methodology and implementing system are provided in which pipelined read transfers or PRTs are implemented. The PRTs include a request phase and a response phase. The PRT request phase involves a PRT request master delivering to a PRT request target, a source address, a destination address and the transfer size for the data being requested. In the PRT response phase, the PRT request target becomes a PRT response master, i.e. a PCI bus master, and initiates a completion of the transaction that was requested in the originating PRT request. Pipelined read transfers are ordered in accordance with a predetermined processing priority to improve performance and avoid deadlocks.

Abstract: The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.

Abstract: An electronic system, precharge circuit, and method for precharging system net. The system includes a plurality of devices. Each of the devices includes at least one I/O pin driven by an driver circuit. The system further includes a system net connected to at least one of the I/O pins of each of the plurality of devices. A precharge circuit suitable for connecting to the system net is provided. The precharge circuit includes a sense stage and a charging stage. The sense stage is configured to receive the system net voltage as an input and adapted to sense a system net voltage transition. The charging stage is connected to the system net and configured to receive an output of the sense stage. The sense stage is configured to activate the charging stage in response to detecting a system net voltage transition. The charging stage, upon activation, is configured to provide a current path between a supply voltage and the system net for a specified duration.

Abstract: Dynamic logic circuits with reduced evaluation time provide faster output in dynamically evaluating logic circuits by increasing the rate of change of the voltage at the junction of logic input ladders. The circuits use a cross-coupled amplifier to charge the input ladder combining node once the node begins to evaluate.

Abstract: In a method and apparatus for reducing parasitic bipolar current in an insulated body, field effect transistor (“FET”), for an n-type FET, the body of the insulated body NFET is electrically isolated, responsive to turning on the NFET. This permits a charge to accumulate on the body in connection with turning the NFET on, temporarily lowering the threshold voltage for the insulated body NFET. Responsive to turning off the insulated body NFET, at least a portion of the charge on the body is discharged. This discharging of the body reduces parasitic bipolar current which would otherwise occur upon turning the NFET back on if the body had charged up during the time when the NFET was off. For a p-type FET that is susceptible to parasitic bipolar current, the body is discharged responsive to turning off the PFET, and isolated responsive to turning on the PFET.

Abstract: A heatsink grounding mechanism and an associated circuit card and computer system. The circuit card includes a printed circuit board to an integrated circuit module is attached. A heatsink is positioned in contact with or in close proximity to the integrated circuit module package. A heatsink grounding piece of the grounding mechanism is utilized to ground the heatsink. The grounding piece includes a substantially rectangular and conductive grounding piece ring that defines an aperture. The dimensions are suitable for receiving and circumventing the integrated circuit module. The grounding piece includes a set of semi-rigid conductive spring arms that extend away from the grounding piece ring. The spring arms are positioned and oriented such that termination points of the spring arms contact grounding pads on the printed circuit board when the grounding piece is compressed between the heatsink and the circuit board.

Abstract: An integrated circuit chip has a first i/o set associated with a first edge of the chip and a second i/o set associated with a second edge of the chip. The first i/o set has a physical symmetry with respect to the second i/o set, to facilitate a number of the chips being interconnected in a ring to one another on a multi-chip module, with the chips symetrically disposed thereon. The chip has a bus interconnecting the first and second i/o sets for transmitting signals across the chip. The bus has regeneration circuitry for regenerating said signals traversing the chip.

Abstract: An apparatus for improving device matching and switching point tolerance in a silicon-on-insulator cross-coupled circuit is disclosed. The silicon-on-insulator circuit includes first and second sets of transistors, first and second rails, and first and second discharge transistors. The first set of transistors is cross-coupled with the second set of transistors. The first rail is connected to each gate of the transistors in the first set, and the second rail is connected to each gate of the transistors in the second set. The body of at least one transistor within the first set of transistors is connected to the first discharge transistor having the same channel type as the connected transistor. The body of at least one transistor within the second set of transistors is connected to the second discharge transistor having the same channel type as the connected transistor.

Abstract: A data processor controlled user interactive display system for displaying hypertext documents, each including a sequence of display screen pages received over a communications network such as the World Wide Web. Each of the pages contains a plurality of hotspots responsive to user interactive pointing means to display a linked document. The system provides display pages in alternate versions wherein only the hotspots on the page are displayed. It includes means for selecting said alternate version for display and means, responsive to said means for selecting, for transmitting said alternate version containing hotspots only to a receiving display station.