Abstract: A method and apparatus for storing and using chipset built-in self-test (BIST) signatures is provided. A BIST for a chip in a data processing system may be initiated by a power-on-reset in the data processing system. The BIST signature generated during the BIST is compared with a predetermined BIST signature stored in a vital products data (VPD) module associated with the chip is read. A difference between the generated BIST signature and the predetermined BIST signature is then reported.

Abstract: Lighting parameters are received as floating-point numbers from a software application via an application programming interface (API). The floating-point numbers are converted to a fixed-point representation having a preselected number of bits. The number of bits is selected in accordance with a predetermined number of bits required by a frame buffer, which thus establishes the number of color values supported by the graphics display system. In order to preserve accuracy to within the number of bits in each value in the frame buffer, the representation in the fixed-point engine includes additional bits relative to the number of bits in the color values sent to the frame buffer. Floating-point values received via the graphics API are converted to fixed-point representations by first prescaling the floating-point values.

Abstract: In a display computer with multiple serial ports, there is provided an on-screen facility for identifying each of the serial ports with a numerical identifier. A process is provided responsive to a change in the status of a connection to any serial port that displays the identifier for that serial port. The change in status takes place when connecting to the serial port. The process may be effectively used in systems having their serial ports extended through a universal serial bus. The identifiers for the serial ports may be stored in a look-up table from which the appropriate identifier may be obtained and displayed upon the connection of a peripheral device to a serial port. Among the many advantages of this on-screen serial port identification is the assurance that the user will not be confused or obstructed by any errors in the physical labelling of serial ports in the manufacture or assembly of computer hardware.

Abstract: A method of verifying a digital circuit in which state transition information is extracted from the output of a non-formal first verification technique. A formal verification tool is then applied to the extracted state transition information to extend the verification coverage of the digital circuit beyond the coverage that is achieved using the first verification technique. In one embodiment, the method includes the initial step of applying a first verification technique such as a simulation technique to a model of the digital circuit. In the preferred embodiment, the application of the formal verification tool comprises applying a model checker to the extracted state transition data to achieve a formal verification of the state machine represented by the state transition diagram. In one embodiment, the extracted state transition information includes a set of data points each representing a present state, a present input, and a next state.

Abstract: A checkstop architecture allows an entire computer system to be immediately halted when a failure(s) or error(s) has occurred at a chip, component, device, sub-system, etc. The present checkstop architecture provides a way of preserving and later providing the state of the computer system at failure or error. The checkstop architecture utilizes a single-wire checkstop that provides a way for quickly stopping all chips in the system and a JTAG that provides a way for querying the error registers in determining which chip pulled checkstop first and what had occurred to cause the error. The present system and method also utilizes a service processor, various computer devices, and at least one central checkstop collection location. The occurrence of the checkstop at one of the computer devices is detected by its internal checkstop operation. The occurrence of the checkstop is driven to the at least one central checkstop collection location, all other of the computer devices, and the service processor.

Abstract: A method and apparatus for detecting an error condition during initialization of a multiprocessor data processing system is provided. A master processor identification indicator is initialized to an initial value by a service processor in the data processing system. The master processor identification indicator may be a location in nonvolatile RAM to protect data integrity. One of the plurality of processors in the multiprocessor system is selected to be the master processor by being released by the service processor and winning the “race condition” to fetch the first instruction from memory for program execution. This processor then sets the master processor identification indicator to a unique processor identification value. The initial value may be a spoof number indicating whether the master processor has yet written its unique processor identification value. At some later point in time, the service processor detects a freeze or hang condition in the data processing system.

Abstract: A method and system for detecting flushed instructions without a flush indicator is provided. In order to monitor the flushing of an instruction in an instruction pipeline of a processor, an instruction is selected as a sampled instruction and the progress of the sampled instruction through the instruction pipeline is monitored. Upon selection of an instruction as a sampled instruction, a countdown value is initialized to a value equal to the maximum number of instructions within the instruction pipeline, and as instructions complete, the countdown value is decremented. If progress of the sampled instruction is detected as the instruction moves through the instruction pipeline, the countdown value is reinitialized. If the countdown value reaches zero, then a flush of the sampled instruction from the instruction pipeline is presumed, and an indication that the sampled instruction has been flushed is generated.

Abstract: The present invention includes a driving circuit and method for driving signals. An input signal is received by the driving circuit on an input signal line which is connected to a bias circuit for a common voltage level. Two output lines from the driving circuit are driven to the receiver which is capable of using differential output lines or a selected single ended output line. Furthermore, the output lines may be driven to a high impedance selected by the voltage level of the input signal. The receiver of the output lines may be a SCSI device using multimode terminators which include low voltage differential and a single ended mode.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: A method and apparatus for selecting an instruction to be monitored within a pipelined processor is presented. One or more pairs of match values stored in control registers are allocated for use in instruction sampling or instruction matching. These pairs, referred to as V0 and V1, are used together to filter instructions for sampling or for instruction matching. During the fetch or decode stage, the instruction word is compared bit by bit to the V0 and V1 pair(s). For each bit in the instruction word, the corresponding bit in V0 and V1 are used to determine if a match exists. If every bit position in the instruction word results in a match, the instruction is eligible for sampling. If any bit position does not match, the instruction is not eligible. In response to a determination that the instruction is eligible for sampling, the execution of the instruction may be monitored.

Abstract: An on-chip clock distribution system and method which utilizes local clock buffers to provide an improved clock signal distribution while avoiding the disadvantages of conventional central buffer and repowered distribution systems. The system also reduces distribution routing problems and distributes “delta-I” problem and thermal problem, and also supports better local delay tuning.

Abstract: A graphics pipeline receives graphics data at an input. Processed graphics data is transmitted at an output of the graphics pipeline. A plurality of stages are present in the graphics pipeline. A first stage within the plurality of stages is connected to the input and a last stage within the plurality of stages is connected to the output. A selected stage within the plurality of stages includes a plurality of modes of operation including a first mode of operation, responsive to receiving a first signal in which the selected stage is enabled to process graphics data received by the stage. A second mode of operation occurs in response to receiving a second signal, the selected stage is disabled and data received from a prior stage within the plurality of stages is passed through to a subsequent stage within the plurality of stages.

Abstract: A method, system, and computer program product for recording events that result from user interaction with the various components of an applet, such as a Java applet. An applet event recorder is invoked and associated with an applet, preferably via a graphical user interface. One or more types of events are then selected for recording via a recording options section of the graphical user interface. When a user interaction sequence with the applet occurs, events of the selected type are then detected by the applet event recorder. An automator of the applet event recorder then generates and stores the queued event objects in an automator queue. The automator then generates, presumably at a later time, constructed events from the queued events in the automator queue. The constructed events are then played back by posting them in the system queue thereby achieving the recording and playback of selected events.

Abstract: A method and apparatus for monitoring an internal queue within a processor, such as an instruction completion table or instruction re-order buffer, is presented. The performance monitoring unit of the processor contains multiple counters, and each counter counts occurrences of specified events. An internal queue of the processor may be specified to be monitored. A count of event signals indicating a successful allocation request for an entry in the internal queue is divided by a count of event signals indicating a passage of units of time to obtain the average rate for allocation requests for queue entries in the specified internal queue. A count of event signals indicating an occupation of a specific entry in the internal queue during a unit of time is divided by a count of event signals indicating an allocation of a specific entry in the internal queue to obtain the average time spent in the internal queue.

Abstract: A texture image that comprises a set of texels wherein each texel is assigned a (u,v) coordinate pair of a texture coordinate space. Each texel is then stored in memory at a memory address determined by applying a transformation function to the texel's (u,v) coordinate pair. The transformation function is customized to associate two dimensional portions of the texture coordinate space to each page of memory. When the texture image (or a portion of the texture image) stored in memory is later mapped to an object during rendering the object, the allocation of two dimensional portions of the texture coordinate space to each memory page reduces the number of memory pages accessed during the rendering of the object. The reduction in the number of memory pages accessed during the texture mapping process translates into improved texture mapping performance.

Abstract: A system and method are provided for detecting when a valid configuration of I/O adapters is present in the system board of a computer. The present invention is a mechanism that allows the system user to determine the configuration of the I/O adapter cards to be used, independent of their voltage levels. More particularly, if the programmed voltage of the computer system power supply is compatible with the desired adapter card, the present invention will allow the card to be inserted and used. The present invention includes a connector that is physically capable of receiving any one of a variety of adapter cards, independent of the operating voltage level of the adapter cards. The present invention is a mechanism for detecting a valid mix of adapter cards inserted into connectors on the system board of a computer. When adapter cards having different voltage ratings are inserted into the slots, power on operations are not allowed preventing possible damage to the computer.

Abstract: A method and apparatus in a data processing system for updating a buffer used to display pixels from a first layer and a second layer in the data processing system, wherein identification display information for pixels from the first layer and the second layer are stored in the buffer. Pixels are identified for the second layer having opaque pixel types to form a selected set of pixels. Overwriting of display information is prevented for the selected set of pixels in the buffer when updating the buffer.

Abstract: A method and apparatus to provide accurate and automated timing of firmware routines, such as initialization tasks at boot time, is provided. Since each task sends a progress indicator code to a display buffer when it starts to run, by saving processor time stamps at the time these codes change, it is possible to calculate and store the time duration for each routine. In the case of system initialization, these time durations can be an indication of problems if they are much longer than normal or an indication of excessive, inefficient, or ineffective processing that might be speed up in order to reduce the total boot time.

Abstract: Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address for accessing a corresponding instruction in a memory device. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.

Abstract: A burst transfer alignment apparatus and method are provided. An interface between the word-aligned subsystem and the double-word-aligned system bus loads a predetermined invalid bit pattern on the system bus corresponding to the second word of the double-word access, in response to a misaligned read. When execution of the predetermined invalid pattern is attempted, an execution exception is thrown. In response the cache line containing the invalid pattern giving rise to the exception is invalidated at the address of the invalid instruction data. Returning from the exception to the address of the invalid pattern, the cache line is refetched. The refetch occurs on an even word boundary, and therefore the refetched cache line transfers properly because the even word address coincides with a double word boundary expected by the bus system.