Abstract: A kerf circuit for modeling of Back End Of Line (BEOL) capacitances is disclosed. The kerf circuit contains a clock circuit connected to a number of capacitance testing circuits. Each capacitance testing circuit acts a “bay” that can be configured to test one particular capacitance. The clock circuit allows the capacitance testing circuits to charge and discharge the capacitive structures being tested. By having a number of different capacitance testing circuits, capacitances of many different structures may be tested at one time. This is particularly true if the kerf circuit is repeated several or many times, with each different kerf circuit containing different capacitive testing circuits that themselves contain different capacitive structures. The kerf circuit interfaces to testing equipment through pads. The pads connect to each capacitive testing circuit and allow capacitance measurements to be performed by measuring current.

Abstract: An FET device and method of making comprising a first dielectric layer; a substrate layer on the dielectric layer; a channel region of a first conductivity type formed in the substrate layer; a gate formed above the substrate layer over the channel region; FET diffusion regions of a second conductivity type formed in the substrate layer, the diffusion regions each having edges, the edges of the FET diffusion regions being separated by the channel region; and a body contact region of the first conductivity type extending continuously from the channel region. The first conductivity type material in the body contact region is thinner than the first conductivity type material in the channel region. The FET also includes a second dielectric layer formed on the body contact region.

Abstract: A linewidth measurement structure for determining linewidths of damascened metal lines formed in an insulator is provided. The linewidth measurement structure including: a damascene polysilicon line formed in the insulator, the polysilicon line having an doped region having a predetermined resistivity.

Abstract: Disclosed is a method of increasing the capacitance of a trench capacitor by increasing sidewall area, comprising: forming a trench in a silicon substrate, the trench having a sidewall; forming islands on the sidewall of the trench; and etching pits into the sidewall using the islands as a mask. The capacitor is completed by forming a node insulator on the pits and the sidewall; and filling said trench with a trench conductor.

Abstract: A grooved planar DRAM transfer device having a grooved gate formed in a groove in a substrate located between source and drain regions. The grooved gate has sidewall portions and a bottom portion which defines a channel therealong. The bottom portion includes a doped pocket such that the threshold voltage Vt on the bottom portion is substantially less than Vt on the sidewall portions, such that the sidewall portions predominantly control electric current through the device.

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions.

Abstract: A method for forming a wirebond connection to an integrated circuit structure includes forming an insulative structure overlaying a corrosion susceptible metal wiring within the integrated circuit structure, defining a via through the insulative structure above a portion of the corrosion susceptible metal without exposing the portion of the corrosion susceptible metal, and attaching a wirebond material to the portion of the corrosion susceptible metal. The attaching process includes a preliminary process of exposing the portion of the corrosion susceptible metal. The attaching completely covers the portion of the corrosion susceptible metal.

Abstract: An anti-fuse structure that can be programmed at low voltage and current and which potentially consumes very little chip spaces and can be formed interstitially between elements spaced by a minimum lithographic feature size is formed on a composite substrate such as a silicon-on-insulator wafer by etching a contact through an insulator to a support semiconductor layer, preferably in combination with formation of a capacitor-like structure reaching to or into the support layer. The anti-fuse may be programmed either by the selected location of conductor formation and/or damaging a dielectric of the capacitor-like structure. An insulating collar is used to surround a portion of either the conductor or the capacitor-like structure to confine damage to the desired location. Heating effects voltage and noise due to programming currents are effectively isolated to the bulk silicon layer, permitting programming during normal operation of the device.

Abstract: A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

Abstract: A method and structure for a bipolar transistor with a semiconductor substrate having a surface and a shallow trench isolation (STI) in the surface. The STI has an edge, a crevice region in the STI adjacent the STI edge, a base region above the STI, a silicide above the base region, an emitter structure on the surface adjacent the base region, and a crevice cover between the emitter structure and the silicide. The crevice cover maintains spacing between the emitter structure and the silicide.

Abstract: A vertically oriented FET having a self-aligned dog-bone structure as well as a method for fabricating the same are provided. Specifically, the vertically oriented FET includes a channel region, a source region and a drain region. The channel region has a first horizontal width and the source and drain regions having a second horizontal width that is greater than the first horizontal width. Each of the source and drain regions have tapered portions abutting the channel region with a horizontal width that varies in a substantially linear manner from the first horizontal width to the second horizontal width.

Abstract: An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.

Abstract: A method and structure for fabricating a dual damascene copper interconnect which electrically contacts a damascene tungsten wiring level. The method forms a first layer on a semiconductor substrate, a silicon nitride layer on the first layer, and a silicon dioxide layer on the silicon nitride layer. The first layer includes damascene tungsten interconnect regions separated by insulative dielectric material. A continuous space is formed by etching two contact troughs through the silicon dioxide and silicon nitride layers to expose damascene tungsten interconnect regions, and by etching a top portion of the silicon dioxide layer between the two contact troughs. A reduced-height portion of the silicon dioxide layer remains between the two contact troughs. The continuous space is filled with damascene copper. The resulting dual damascene copper interconnect electrically contacts the exposed damascene tungsten interconnect regions.

Abstract: A semiconductor device is presented which is composed of two adjacent semiconductor chips. Each semiconductor chip has an integrated half-wave dipole antenna structure located thereon. The semiconductor chips are oriented so that the half-wave dipole antenna segments extend away from each other, allowing the segments to be effectively mated and thus form a complete full-wave dipole antenna. The two solder bumps which form the antenna are separated by a gap of approximately 200 microns. The length of each solder bump antenna is based on the wavelength and the medium of collection. Phased array antenna arrays may also be constructed from a plurality of these semiconductor chip antennae.

Abstract: Off-current is not compromised in a field effect transistor having a gate length less than 100 nanometers in length by maintaining the conduction channel width one-half to one-quarter of the gate length and locating the gate on at least two sides of the conduction channel and to thus create a full depletion device. Such a narrow conduction channel is achieved by forming a trough at minimum lithographic dimensions, forming sidewalls within the trough and etching the gate structure self-aligned with the sidewalls. The conduction channel is then epitaxially grown from the source structure in the trough such that the source, conduction channel and drain region are a unitary monocrystalline structure.

Abstract: Disclosed is a semiconductor device comprising: a multiplicity of wiring levels, each wiring level comprising conductive wires and a multiplicity of conductive fill shapes embedded in a dielectric; at least some of the fill shapes in at least two adjacent wiring levels being co-aligned; and where the fill shapes on adjacent levels are aligned, one or more conductive vias extending between and joining each co-aligned fill shape in each adjacent wiring level. The joined fill shapes serve to reinforce and support the dielectric, which may be a non-rigid or low-k dielectric.

Abstract: An SOI multiple FET structure is provided that comprises a substrate having a substrate layer on an insulator layer. The SOI multiple FET structure includes distal diffusion regions in the substrate layer and a central diffusion region in the substrate layer. The central diffusion region has a width and extends from a surface of the substrate layer downward into contact with the insulator layer along a portion of the width and extends only partially into the substrate layer along another portion of the width. The SOI multiple FET structure also includes a pair of gates on the surface of the substrate layer each overlapping one of the distal diffusion regions and the central diffusion region; and a pair of body regions in the substrate layer each under one of the gates for forming a channel between the one of the distal diffusion regions and the central diffusion region. The body regions are in electrical communication under the another portion of the width of the central diffusion region.

Abstract: A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal propagation paths between devices formed on respective wafer layers of a chip. In preferred embodiments, an SOI wafer is formed by hydrophilic bonding of a wafer over an integrated circuit device and then cleaving a layer of the second wafer away using implanted hydrogen and low temperature heat treatment. Further wafers of various structures and compositions may be bonded thereover and connections between circuit elements and connection pads in respective wafers made using short vias that provide fast signal propagation as well as providing more numerous connections than can be provided on chip edges.

Abstract: A method is provided to preferably create robust contacts and interconnects by depositing a thin layer of a first conductive material on a wafer through a non-ionized deposition process. The thin layer overlays the wafer and lines any apertures in the wafer. Deposition of a first conductive material is followed by depositing another thin layer of a second conductive material by an ionized deposition process. In this manner, the second conductive material overlays the first conductive material and additionally lines the wafer and any apertures in the wafer. Furthermore, if the apertures open to underlying areas, the conductive materials that line the apertures preferably create a conductive film that can form a plurality of contacts between the conductive film and the underlying areas.

Abstract: A data processing system that automatically changes a semaphore in response to a test and set or clear and invalidate instruction. When a device desires to either test and set or clear and invalidate a semaphore, it transfers an instruction having a test and set or clear and invalidate operation code and the address of the semaphore over the bus. The device responsible for managing the semaphore receives the instruction and automatically changes the semaphore. Therefore, a device is only required to transfer the instruction to test and set or clear and invalidate the semaphore. Moreover, because the test and set operation requires only a single instruction transfer, special techniques are not necessary to insure exclusive access to the semaphore during the operation.