Abstract: A computer assembly is described. The computer assembly includes a motherboard and a socket mounted to the motherboard. The socket, which enables the motherboard to receive a memory card, has a mounting pin that is inserted into a via that is formed in the motherboard. A stub trace is coupled to the via to add capacitance at the via.
Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, then forming a capping layer on the high-k gate dielectric layer. After oxidizing the capping layer to form a capping dielectric oxide on the high-k gate dielectric layer, a gate electrode is formed on the capping dielectric oxide.
Type:
Grant
Filed:
March 18, 2003
Date of Patent:
February 24, 2004
Assignee:
Intel Corporation
Inventors:
Justin K. Brask, Mark L. Doczy, John P. Barnak, Robert S. Chau
Abstract: A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.
Type:
Grant
Filed:
October 31, 2002
Date of Patent:
February 10, 2004
Assignee:
Intel Corporation
Inventors:
Christopher G. Parker, Markus Kuhn, Ying Zhou
Abstract: A method of converting a hydrophobic surface of a dielectric layer to a hydrophilic surface is described. That method comprises forming a dielectric layer on a substrate, then operating a PECVD reactor to generate a plasma that converts the surface of that layer from a hydrophobic surface to a hydrophilic surface. Also described is a method for making a semiconductor device that employs this technique.
Abstract: A method of making an on-die decoupling capacitor for a semiconductor device is described. That method comprises forming a first barrier layer on a conductive layer. The upper surface of the first barrier layer is modified to enable a dielectric layer with an acceptable nucleation density to be formed on the first barrier layer. A dielectric layer is formed on the first barrier layer, and a second barrier layer is formed on the dielectric layer.
Abstract: A semiconductor device and an improved method for making it are described. The semiconductor device comprises a dual damascene interconnect that includes a conductive line. The device further includes a support structure that is spaced from the conductive line, and an insulating layer that is formed on the support structure and the conductive line. In the method for forming that device, a support structure is formed on a substrate, and an insulating layer is formed adjacent to it. Portions of the insulating layer are removed to form a via and a trench, which are filled with a conductive material to generate a dual damascene interconnect that includes a conductive line, wherein the conductive line is spaced from the support structure.
Abstract: An improved method for making an integrated circuit. That method includes forming a first dielectric layer on a substrate, etching a trench into that layer, then filling the trench with a conductive material. The conductive material is then electropolished to form a recessed conductive layer within the first dielectric layer.
Abstract: A method and apparatus for reducing the disk drive data transfer interrupt service latency penalty is described. The method comprises beginning a data transfer between a disk drive and a host system, issuing an interrupt before the transfer is complete, and then completing the data transfer. This method may be implemented on a computer assembly that includes a processor, an input/output controller, and a scatter/gather list, which is stored in memory, that includes an entry that will cause the input/output controller to generate the interrupt.
Abstract: A method for making a semiconductor device is described. That method comprises forming a carbon doped oxide containing layer and a dielectric layer on a substrate, such that at least part of the dielectric layer is located above at least part of the carbon doped oxide containing layer. A chemical mechanical polishing process is then applied to remove the part of the dielectric layer that is located above the part of the carbon doped oxide containing layer, such that it removes the dielectric layer at a significantly faster rate than it can remove the carbon doped oxide containing layer.
Abstract: A system and method for securing configuration information for a computer system. The method comprises saving configuration information in CMOS memory and automatically programming that configuration information into a non-volatile memory. The system includes a processor, a CMOS memory, and a flash memory. The system also includes a computer-readable medium having computer-executable instructions stored therein for causing configuration information, when saved to the CMOS memory, to be automatically programmed into the flash memory and for causing configuration information stored in the flash memory to be automatically retrieved from the flash memory and written into the CMOS memory every time the computer system is powered on or reset.
Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. The dielectric layer is modified so that it will be compatible with a gate electrode to be formed on the dielectric layer, and then a gate electrode is formed on the dielectric layer.
Type:
Grant
Filed:
February 22, 2002
Date of Patent:
September 9, 2003
Assignee:
Intel Corporation
Inventors:
Robert Chau, Reza Arghavani, Mark Doczy
Abstract: A method for making a semiconductor device is described. That method comprises forming on a substrate a dielectric layer that has a dielectric constant that is greater than the dielectric constant of silicon dioxide. An insulating layer, which is compatible with the dielectric layer and a gate electrode to be formed on the insulating layer, is formed on the dielectric layer, and a gate electrode is then formed on the insulating layer.
Abstract: A method of forming a carbon doped oxide layer on a substrate is described. That method comprises introducing into a chemical vapor deposition apparatus a source of carbon, silicon, boron, and oxygen. That apparatus is then operated under conditions that cause a boron containing carbon doped oxide layer to form on the substrate.
Abstract: A method of forming a semiconductor device is described. In that method, a masking layer is formed on a substrate. A layer of photoresist is then deposited and patterned on that layer to expose a first part of the masking layer while covering a second part of the masking layer. After the exposed part of that layer is etched, the resulting device is exposed to a plasma generated from a forming gas. Part of the second part of the masking layer is then removed by exposing the resulting device to a solution, while part of the second part of the masking layer is retained.
Abstract: A method of making a semiconductor device is described. That method comprises forming a copper containing layer on a substrate, introducing a void nucleation site into the copper containing layer, and forming a via that is located a distance removed from where the void nucleation site was introduced into the copper containing layer.
Abstract: A semiconductor manufacturing a method and an apparatus is described. That apparatus includes an ash chamber that has an ash chamber base, and a heating unit that is coupled to the ash chamber base. The heating unit applies heat to the ash chamber base to reduce deposition of residues onto ash chamber base surfaces, which could cause surface particle defects in a semiconductor device.
Abstract: A method and apparatus for initializing a computer system, which includes a lockable nonvolatile memory coupled to a processor having maskable address lines and a cache, when a nonvolatile memory update is in process. When an update is in process, the nonvolatile memory is unlocked in response to the initialization event only if address line masking is disabled, and at least a portion of the processor cache is invalidated to ensure the processor will fetch the first instruction from the nonvolatile memory.
Type:
Grant
Filed:
December 20, 1999
Date of Patent:
May 13, 2003
Assignee:
Intel Corporation
Inventors:
Robert P. Hale, John V. Lovelace, Christopher J. Spiegel
Abstract: A method for making a semiconductor device is described. That method comprises forming a carbon doped oxide containing layer and a dielectric layer on a substrate, such that at least part of the dielectric layer is located above at least part of the carbon doped oxide containing layer. A chemical mechanical polishing process is then applied to remove the part of the dielectric layer that is located above the part of the carbon doped oxide containing layer, such that it removes the dielectric layer at a significantly faster rate than it can remove the carbon doped oxide containing layer.
Abstract: A continuity module for a memory channel for a computer system. The continuity module includes a connecting member for coupling the continuity module to a socket that is coupled to a motherboard. The continuity module also includes a printed circuit board, which is coupled to the connecting member. The printed circuit board includes a signal trace that is coupled to a capacitive load. In preferred embodiments, the capacitive load comprises a plurality of vias and/or stub traces, which are coupled to the signal trace.
Abstract: A method for making a photolithographic mask. The method comprises forming a film on a substrate that deforms the substrate, and applying a deformation reducing agent to the substrate to reduce the amount of deformation that the film caused. In a preferred embodiment, the deformation reducing agent comprises one or more films, which are formed on one side of the substrate, that balance the substrate deformation effect of one or more films that are deposited on the other side of the substrate. The film or films that constitute the deformation reducing agent may be similar to, or different from, an absorption film and/or any other films deposited on the substrate or on the absorption film.
Type:
Grant
Filed:
March 14, 2000
Date of Patent:
March 25, 2003
Assignee:
Intel Corporation
Inventors:
Qing Ma, Jin Lee, Jun Fei Zheng, Giang Dao