Abstract: A system for and a method of generating a four phase clock signal is disclosed. The system includes an oscillator circuit that generates a clocking signal of frequency F. A flip-flop, under control of a Master Clear signal, establishes the first stage of a shift register in an active state while the clocking signal drives the shaft register to serial, end-around, shift the active state through the shift register. The parallel outputs of the shift register are coupled to respectively associated pulse generators which are also triggered by the clock signal to emit the four phase clock signal therefrom. The method ensures that the first phase signal is always the first signal to be emitted from the system while compatible semiconductor circuitry is used throughout and is operated at or near the frequency limit of the semiconductor circuitry used.

Abstract: A large capacity (8 memory banks of 524K error-corrected 36 bit words stored) high performance (latency as low as 240 nanoseconds, 12.8 gigabits/second aggregate data transfer capability with up to 11.4 gigabits/second utilized) pipelined (8 deep request pipeline) random access memory store simultaneously (to the limit of bank addressing conflicts) services intermixed requests from an internal exerciser plus ported requestors (up to 10) of plural types (3 types), which requestors are not of the same interface cycle time (30 nsec vs. 60 nsec). Furthermore, to such nonuniform interface cycle times, the bit-width of the data transfer interfaces (ports) to the requestors of plural types is also not uniform, but is actually wider (4 interface words of 36 bits each=144 bits) to faster (30 nanosecond) requestors than is that data transfer bit-width (2 interface words=72 bits) to slower (60 nsec) requestors.

Abstract: An economical circuit of n transistors and m resistors (n=4, m=1 for Emitter Coupled Logic (ECL); n=3, m=0 for Current Mode Logic (CML)) interconnects to a fast differential feedback latch of r transistors and s resistors (r=12, s=9 for ECl; r=7, s=3 for CML) using two levels of series gating and one current source in order to establish scan/set testability of such latch. An additional interconnected circuit of v transistors and w resistors (b=2, w-1 for ECL; v=1, w=0 for CML) further establishes either a reset or a set capability for such latch. The economical total scan/set testable latch of x transistors and y resistors (x=18, y=11 for ECL; x=11, y=3 for CML) exhibits an excellent delay-power product since a single current is selectively steered into one of four different paths, the remaining three of which paths are shut down. Use of but a single current source provides further economy of silicon implementation.

Abstract: A system for accelerating the granting of prioritized memory requests to a multi port memory system of a data processing system is disclosed. The priority requestor accelerator system detects the fact that one remaining requestor is in the priority memory system. The priority system logic is cleared out before the end of the normal requestor cycle. This allows the acceptance of a new set of requestors to be presented to the priority circuits at that time rather than waiting until presentation of the final request. Thus, the accelerator detects that the requestors from a previous requesting snap are on their last cycle. This allows a preclearance of the lower ranks as the priority circuit finishes its last cycle. The new requests are then loaded and the priority inputs are snapped shut beginning a new set of cycles. The overall operation happens as if the priority circuit is just moving from one requestor to another that is already in residence after the snap.

Abstract: Transmitting and receiving apparatus for transmitting data includes a purged code encoder at the transmitter for encoding digital data into constant weight unbalanced codewords representative of the digital data. The constant weight unbalanced codewords containing error correction bits are preferably transmitted as balanced codewords and are decoded at the receiver employing Golay decoders or algebraic decoders to recover the original digital data without the requirement of a large number of matched filter previously employed for decoding.

Abstract: A method of fabricating a thin magnetic film having improved magnetoresistive readout characteristics as a binary memory device is disclosed. The film is initially formed from a metal vapor as a series of discrete grains upon a substrate surface that is heated to approximately 300.degree. C. Upon continued growth of the film, the grains merge at their boundaries forming a continuous thin film, the grain boundary heights of which, e.g., 1000 .ANG., are substantially greater than the thickness, e.g., 320 .ANG., of the eventual thin magnetizable film. The thin film is then rotated while being ion milled at an oblique angle to a substantially uniform film thickness of e.g. 320 .ANG..

Abstract: A lockable compliant end effector apparatus is useful with a robotic arm for the automated assembly of electronic equipment. The end effector includes a main body portion having first and second ends. A socket is formed in the first end. A first fluid passageway connects the socket with the second end of the main body portion. A member is mounted for multi-directional movement in the socket. The member is retainable in a stationary position relative to the socket and has a second fluid passageway formed therethrough. The second passageway has a first end adjacent the first passageway and a second end adjacent the first end of the main body. A sealing member is connected to the mounted member adjacent the second end of the second passageway. The end effector retains an electronic component in original orientation from a pickup point to an insertion point.

Abstract: A high performance pipelined virtual first-in first-out stack structure has a data stack portion and a split control stack portion. The stack structure is intended for use in a pipelined high performance storage unit that can pipeline up to R input requests without having received an acknowledge that a request has been honored. The data stack incorporates R+1 data stack registers to provide over-write protection to ensure that at least R data stack registers are protected from over-write. The split control stack utilizes even address and odd address stack registers. Memory bank request signals are stored sequentially and alternately between the even address and odd address stack registers.

Abstract: The problem of re-establishment of initial precision registration of end-effectors used in automatic robotic assembly following failed insertion attempts is avoided due to a positive registration compliant apparatus having a support member including a bearing mount spaced apart from a shaped seat. A holder for holding and mounting electronic components is movably mounted on the support member and extends through the bearing mount. The holder has a portion correspondingly shaped for mating engagement with the shaped seat. The holder is resiliently urged into engagement with the seat. A rotation limiter is provided for limiting rotation of the holder relative to the support.

Abstract: A method and apparatus of offset correction which can be applied to control systems, primarily phase-locked-loop systems, and which permits sampling of the error signals for use as an auxiliary input to the system in order to center the error signal around zero.

Abstract: A video display control circuit, for an intelligent terminal, includes a large cost efficient Random-Access Memory (RAM). A portion of the RAM memory is utilized as a high speed character generator instead of employing a dedicated Read Only Memory (ROM). Novel timing and memory control circuits are provided which permit characters to be generated witout any delay or change of real character timing. The characters in RAM may be modified or changed which is not possible with dedicated Read Only Memories.

Abstract: A high speed system utilizing programmably controlled ranks of multiplexers for reformatting data from programmably selected first formats to second formats is described. Interleaved input data is utilized to optimize reformatting rates. The reformatting system provides field selection and justification together with the capability of complementing and magnitude generation of the selected fields. Floating-point operands in two different floating-point formats can be unpacked, that is the characteristic separated from the mantissa and properly aligned, and can be packed by positioning and recombining the characteristic with that associated mantissa. Throughout the entire reformatting process, parity for selected bit groupings is maintained, thereby allowing through checking of reformatting operations. The reformatting system includes programmably selectable constant generation.

Abstract: A binary division circuit for use in a large data processing system is disclosed which performs division with floating or fixed point numbers. It includes a multiplier unit which is modified to produce the higher precision calculation necessary to the division operation. This modification includes an augmented multiplier circuit which is combined with a quotient correction technique to provide a binary division circuit which produces identical quotients to those obtained by restoring or non-restoring divide techniques in less time than is required by other divide techniques.

Abstract: An improved masked arithmetic logic unit is disclosed which incorporates at least three principle unique features to optimize implementation in a high speed environment. These features are (1) the inclusion of a mask operand to facilitate mask compares and mask substitute operations without adding logic levels to the arithmetic logic unit; (2) the inclusion of a sum minus one network to speed up system performance by minimizing the delay usually associated with group borrow input to final sum output and (3) the inclusion of a mode control register internal to the arithmetic logic unit to minimize or camouflage the delay always found in the mode switching control of contemporary arithmetic logic units.

Abstract: A novel high speed gallium arsenide depletion mode field effect transistor logic circuit is provided. One logic input is connected to the source electrode of the switching transistor and draws current when a low level input voltage is provided. Other logic inputs are connected to the gate electrode of the switching transistor and supplies current when a high or low level input voltage is provided. The novel logic output from the source electrode of the switching transistor is a complex OR function which may be employed for a logic family having fewer stages of logic than prior art gallium arsenide circuits.

Abstract: The memory system incorporates a memory element storing binary digital data in the presence, vel non, of a Y-domain cross-tie. The memory element has a planar contour that is substantially symmetrical about a longitudinal axis and that has edge portions that are nowhere perpendicular or parallel to the longitudinal axis. A stabilizing magnetic field applied perpendicular to the longitudinal axis and in the plane of the memory element forms a first Neel wall along the longitudinal axis and causes the magnetization in the memory element to be formed into first and second domains on opposite sides of the Neel wall. When a writing magnetic field oriented in the plane of the memory element and perpendicular to the longitudinal axis but opposite to the stabilizing magnetic field orientation is coupled to the memory element, there is formed in the memory element a third domain separated from the first and second domains by second and third Neel walls having a join with one end of the first Neel wall.

Abstract: An apparatus for maintaining electronic component pin alignment includes a support member having an adjacent lead shear, a stationary nest, a printed circuit board and a component feeder. A component in the component feeder includes a chip having a plurality of leads. The leads have a first end connected to the chip and a second free end. A movable lead guide engages the first end of the leads. A robot is mounted adjacent the support member for picking up the component from the component feeder, inserting the component into the stationary nest moving the component relative to the stationary nest for moving the lead guide from the first end of the leads toward the second free end of the leads, moving the component from the stationary nest to the shear for shearing the second free end of the leads, and moving the component from the shear to the printed circuit board and urging the leads into corresponding holes formed in the printed circuit board.

Abstract: A novel maximum likelihood sequence detector is provided for decoding linear cyclic error correction codes. The detector comprises one cyclic correlator for each two shaft sets of the code which have weights greater than one, and a serial correlator for detecting the shift sets of all zero's and all one's. The number of cyclic correlators required to decode linear codes is reduced to less than half the number of shift sets which define all the codewords instead of half the number of codewords where the number of shift sets is always less than the number of codewords.

Abstract: A disc is firmly clamped to the end of a rotatable spindle by a coaxial clamping plate spaced from the spindle end by a ring between the plate and disc surface and attached to the spindle by a single coaxial bolt. The flexible plate, thicker at its center than near its periphery, has a substantially flat inner surface which, when stressed by tightening of the bolt, is deformed without exceeding its yield stress to the point where its center section contacts the spindle end surface to provide a constant predetermined clamping force evenly around the disc.The disc and spindle assembly is rapidly and accurately balanced without loosening the clamped disc from the spindle with an adjustable balancing bar which is attached to the head of the coaxial bolt and which may be properly adjusted by the use of a conventional balancing system which can indicate magnitude and direction of the imbalance.

Abstract: An integrated circuit package having an auxiliary heating element incorporated therein is described. The integral heating element is accessible for application of electric power from an external source to cause heating of the integral circuit package to a predetermined level at which solder will melt and flow, thereby allowing removal and reinsertion of the integrated circuit package with relationship to associated pins in a support assembly. The integral heating element provides a means for applying controlled heat to the integrated circuit package such that the package can be unsoldered from or soldered to associated electrical interconnection pins, some of which may be hidden from view or physical access.