Abstract: A high gain Josephson junction logic circuit is provided. The novel circuit comprises a high gain non-linear threshold input Josephson junction logic circuit which is coupled to a high gain Josephson junction amplifier. The high gain input circuit provides the capability of driving a larger number of output circuits or employing a larger number of input signals.

Abstract: A 72-bit shift matrix, suitable for LSI implementation in gate arrays, is disclosed. Eight byte shifters and eight bit shifters are combined to produce shifts of 0-72 places in either direction, circularly or open ended with zero or sign fill. A means is additionally provided to regenerate original source parity from the matrix outputs for use in thru checking. A single 9-bit parity generator is all that is required to check the correctness of the matrix.

Abstract: A level sensitive scan design (LSSD) Latch Cell that is adaptable to very large scale integrated (VLSI) Semiconductor circuit fabrication is disclosed. The Latch Cell includes a static functional latch and a dynamic test latch, both of which are controlled by a data selector that selects input data from either a functional data source or test data from another test latch in a scan data path.

Abstract: An integrated circuit chip is cooled by being mounted on a substrate which is urged into contact with a compliant mat which includes a layer having a predetermined array of interconnected metallic pads for spreading heat flux more uniformly. The mat is connected to a plate which may be water cooled. The mat also includes additional layers which are heat conductive and electrically insulative. One of the additional layers is a film of paste.

Abstract: A multiply pipeline with parity circuit to be used as a building block in a multiplication pipeline of arbitrary size is disclosed. It includes circuits for generating and checking parity. The parity of the output carries leaving the component chips of the multiply pipeline are explicitly generated internally to those chips. By generating output carry parity on-chip, all single-bit errors except for those caused by on-chip internal gate or metallization faults will be detected. Thus, means are provided for detection of single-bit errors in the multiplication circuitry. The proposed multiply pipeline with parity circuit includes a pair of gate arrays, or chips, which participate as follows. A 6-bit by 6-bit multiply with parity chip is used as a building block in a portion of the pipeline in which all logical products are initially generated, and reduction of these logical products, or partial products, commences.

Abstract: During the assembly of electronic components on circuit boards, the problems of ductile smear cusps produced on wire ends by traditional scissor-type shearing are addressed by a spiral orbital shear apparatus. This apparatus includes a first fixed plate having an array of apertures and a second plate also having the array of apertures. The first and second plates have abutting surfaces. A first eccentric drive member is connected to rotate at a first rate in a first direction. A second eccentric drive member is connected to the second plate and rotates with the first eccentric drive member. The second drive member is also rotated at a second rate in the first direction independently of the rotation of the first drive member.

Abstract: Circuitry for distinguishing each value in a read signal magnetically recorded in ternary-3 position modulation in which the values 1, 2 and 0 are detected and equalized into a singlet, a doublet and absence of magnetic flux change. The circuitry first determines the position locations of each singlet peak and doublet crossover point to establish proper timing of the output signals and then identifies the particular type of signal appearing at the timing points in the read signal sequence. Singlets are identified by the much greater amplitudes in the integrated read signal. Doublets are identified as waveforms having slopes at zero crossovers that correspond in polarity to that of the previous singlet. A novel detector circuit is provided that can correctly identify doublets in a code sequence, irrespective of the presence of a previous singlet, when a recording rule is followed that includes the insertion of a number of consecutive ternary 0 symbols into the recorded signal.

Abstract: A low insertion force connector for making electrical connection between electrical contacts on a printed circuit board assembly and external circuitry, and having an improved linear cam actuating mechanism is described. An elongated outer housing having a centrally located opening with a longitudinal channel along the bottom thereof, has spaced apart ramps positioned at the bottom of the channel. The housing has an aperture at each end thereof, and has external ramps on each end of the outer housing in a predetermined relationship to the associated aperture. A plurality of contacts are mounted within the outer housing on either side of the channel, with first ends interior the housing being bowed inwardly for contacting the printed circuit board assembly, and second ends extending through said outer housing for making electrical connection to external circuitry.

Abstract: A decoder for forward-error-correcting (FEC) convolutional codes. The decoder uses the Viterbi algorithm for decoding the rate 1/2, constraint length 7 code with generator polynomials x.sup.6 +x.sup.5 +x.sup.3 +x.sup.2 +1, and x.sup.6 +x.sup.3 +x.sup.2 +x+1. The architecture of the instant decoder is appropriate for implementation on a single, monolithic VLSI integrated circuit chip and includes a branch metric calculator circuit which produces output signals representative of input symbol signals. These output signals are supplied to a metric update circuit which evaluates the signals from the calculator circuit and provides decisions to a path update circuit which converges the signals thereto and the output signals of which are evaluated by a majority vote circuit which produces data output signals representative of data input signals.

Abstract: A shell for a connector for flat shielded cable. The shell is formed of conductive material and is constructed so as physically and electrically to contact the shield so that grounding the shell will ground the shield. The shell also includes portions to grip firmly the cable so as to relieve strain from the cable-connector connection. Finally the shell defines a cavity for the connector; the cavity has one or more irregularities corresponding to mirror image irregularities in the connector cavity to assure proper positioning of the connector within the shell cavity. Associated with the receptacle adapted to receive the connector are two toggle latches; the shell is provided with external hooks adapted to cooperate with the toggle latches so as to achieve firm connection between the connector and the receptacle as well as connection of the shell to ground.

Abstract: Apparatus for producing a circular-queue structure which permits interfacing between a high speed mini-computer and a relatively slow speed microprocessor via a common memory and with multi-device, asynchronous handling capability. The structure also permits commands and data to be chained in the same queue. The apparatus permits multiple devices to be handled simultaneously. By monitoring the memory address which is being accessed by the minicomputer, the information retrieved from the memory by the microprocessor is selectively validated or invalidated.

Abstract: A novel multilayer lift-off pattern of positive and negative photoresist materials is provided. A positive first layer is deposited on a substrate and flood exposed before a subsequent layer of negative photoresist material is added on top of the positive photoresist material. An optional third layer of positive photoresist material may be added on top of the negative photoresist to provide the top layer. A window or aperture is provided in the top layer employing conventional mask, exposure and development techniques. The top of the bottom layer is plasma etched through the window or aperture so that the previously flood exposed bottom layer can be developed without affecting the layers deposited thereon. A deep undercut lift-off pattern is provided which is useful in the manufacture of Josephson junction devices employing low temperature metals as well as for the manufacture of semiconductor devices.

Abstract: For use with a digital memory system that generates error correction code signals for storage with associated data words and for correction of detected error(s) in the associated data words when accessed, a system for through checking the accuracy of generation of the error correction codes and the decoding of error correction code is described. A data word parity signal is generated for storage with the associated data word and its associated check bit. When a data word is accessed, the read data word and its associated check bits are applied to error correction circuitry that results in a determination of whether or not any bits of the read data word are in error. Correction circuitry corrects those error in the read data word that are correctable. The corrected read data word is applied to a parity generator circuit that generates that parity of the corrected read data word. A comparison circuit compares the word parity calculated for the corrected read data word.

Abstract: This invention is a device to reduce the wobble of a rotating shaft disposed in a cavity of a housing which wobble results from a spurious or undesirable positioning of a bearing assembly in which the shaft rotates. The present device includes a bearing follower which is shaped to have a long side which is in abutment with the side walls of the cavity. Accordingly, the follower cannot be readily placed in a cocked or misaligned position. The follower is spring loaded against the bearing assembly which is subject to being cocked and thereby reduces the capability of that bearing assembly to be misaligned.

Abstract: A method and a means are disclosed for the throughchecking of the normalizer operations of an arithmetic unit of a data processing system involving both integer and floating-point formats in single and double precision operations. A post normalizer is used in conjunction with the main normalizer of the arithmetic unit to determine if the result is indeed normalized. Where the post normalize count is zero, an error designator remains inactivated. However, where the count is non-zero, the error designator is activated to indicate an error exists, unless it is disabled by separate circuitry which detects that the number being shifted is .+-..0.. The preferred embodiment disclosed herein checks the operation of a pair of 72-bit main normalizers with a single 13-bit post normalizer. A plurality of instructions in which this check is significant are illustrated.

Abstract: An improved dynamic memory system including through-checking and error detection of the refresh counter is described. A refresh counter that provides parity of the refresh count for through-checking, of refresh addresses is shown. Error detecting circuitry is utilized in conjunction with the refresh counter and the parity generating circuitry to detect errors in functionality of the refresh counter. The refresh counter is a Gray code counter constructed of a double rank of latches operable with code generating logic circuits for determining the sequence of generation of Gray code groupings.

Abstract: A unique memory management system for use with a memory device which is common (or shared) with a plurality of user elements utilizing a memory address counter, scratch pad address memory, external memory address inputs and an address multiplexer.

Abstract: A clock source for timing and synchronizing the operation of digital data processing equipment and having automatic duty cycle correction is described. A source of signals provides clock signals at a predetermined frequency. A buffer circuit provides the true and complement clock signals to low pass filters that function to filter the true and complement clock signals to DC levels proportional to the duty cycle of the source signals. The DC voltages represent instantaneous deviation voltages from a known reference and are applied to a differential amplifier circuit for providing a feedback signal for adjusting the duty cycle of the clock output pulses that are available. One embodiment has the source of signals directly coupled to the buffer circuitry and utilizes the feedback signal to adjust the duty cycle of the signal source circuitry. A second embodiment has the source signals capacitively coupled to the self-correcting circuitry and the feedback signals adjust the duty cycle of the clock output signal.

Abstract: An improved error indicating system utilizing adder circuits for use with an error correction code system capable of detecting and indicating multiple bit errors and detecting and correcting single bit errors is described. The system utilizes an encoding system for generating a plurality of check bits, each check bit associated with a predetermined bit grouping of data bits within a data word. When a data word is accessed, read check bits are reconstituted from the read data and are compared to the check bits originally encoded. Syndrome bits are generated from the originally encoded check bits and the reconstituted read check bits, the syndrome bits thus generated, serving to identify whether the data word accessed contains no errors, a single bit error, or a multiple bit error. Decoder circuitry for decoding the syndrome bits and effecting the control signals for controlling the correction of single bit errors is described.

Abstract: A high speed multiplier circuit is disclosed which not only provides increased performance for the multiply operations of a large scale processor but also provides for single bit error detection of results as well. It incorporates a gated carry/save adder array to eliminate the decoding of multiplier characters thereby reducing logic levels and enhancing performance. A means is illustrated for detecting single bit errors without redundancy or performance loss. While the array proper is more complex than other multibit algorithms, the multiplexers needed by those earlier systems are no longer required. The small increase in complexity of the array proper eliminates the need for decoding of the multiplier bits or other interaction between the multiplier groups. The net effect is a reduction in logic with faster operation because of the omission of the decoding requirement.