Abstract: A multi-level cell (MLC) dual-personality extended fiber optic flash drive includes a MLC dual-personality extended fiber optic Universal Serial Bus (USB) plug connector connected to a dual-personality extended fiber optic flash drive and being removably connectable to a host. The connector is adaptable to receive electrical data and optical data. A transceiver, located on the flash drive, is operative to convert received electrical data to optical data or to convert received optical data to electrical data.

Abstract: A enterprise security management (ESM) system having a web-based platform for authorizing and monitoring visitors of a secure facility and for further providing a time-stamping process for noting the time of arrival and departure of the visitors and for alerting authorities when the duration of stay of a visitor has exceeded the predetermined time for visiting allotted the visitor.

Abstract: A modem system for transmitting and receiving signals having a frequency domain equalizer (FEQ) being responsive to a plurality of received data symbols for processing the same to generate one or more equalized data symbols, said modem system being responsive to a plurality of received baseband signals for processing the same to generate said plurality of received data symbols, said plurality of received data symbols for including one or more sets of pilot tones, said FEQ for processing said sets of pilot tones to generate one or more sets of equalized sets of pilot tones, in accordance with an embodiment of the present invention.

Abstract: A Universal Serial Bus (USB) flash drive includes a slim USB device having an end used to couple the USB flash drive to a host and an opposite end, and a swivel “strap shaped” metal cap having a circle cut out disposed on both cap legs. The snap coupling circle attachment allows the swivel cap to rotate substantially into a first and a second locking position and to rotate substantially 360 degrees about the z-axis of the USB device. The metal cap is generally in a locked position when the snap slot is aligned atop the snap lock tabs such that the protrusion snap ring is descended downward until the positioned flush against the snap lock groove. When unlocked the protrusion snap ring is raised up and rested upon the two snap lock tabs.

Abstract: A switch is coupled between a plurality of host units and a device for routing frame information therebetween. The switch includes a first serial advanced technology attachment (ATA) port including a first host task file that is responsive to a non-data frame information structure (FIS) from a first host unit. The switch further includes a second serial ATA port including a second host task file that is responsive to a non-data FIS from a second host unit. The switch further includes a third serial ATA port that is responsive to a non-data FIS from a device and further includes an arbitration and control circuit for selecting one of the first host or second host units to concurrently access the device, through the switch, by accepting non-data FIS, from either of the first or second host units, at any given time, including when the device is not in an idle state.

Abstract: A hard disk drive is coupled to a plurality of host units for communication. The first host unit includes a serial advanced technology attachment (SATA) port, including a first host task file coupled for access to the device and responsive to commands sent by the first host unit. The second host unit includes a SATA port, including a second task file, coupled for access to the device and responsive to commands sent by the second host unit. An arbitration and control circuit is coupled to the first host task file and second task file. The arbitration and control circuit selects commands from one or the other host units when either host units sends a command for execution for concurrently accessing the device, and accepts commands from both, at any given time, including when the device is not idle.

Abstract: Briefly, an embodiment of the present invention includes a portable flash memory drive with a simplified mechanism, based upon the resilient properties of the material used to create the parts, for reliable extension and retraction of the device's interface plug. The portable flash memory drive is comprised of a metal housing (or case), a printed circuit board (PCB) assembly, PCB support, PCB assembly end cap, an upper, and lower housing, and in some embodiments a fingerprint sensor and/or key ring assembly. The press/push switch mechanism is located on either the side of the portable flash memory device, or the top; and relies upon the resilient properties of the material used to create the metal housing or end cap, to create a smooth, locking mechanism for the extension or retraction of the interface (i.e., USB or firewire) plug.

Abstract: A switch is coupled between a plurality of host units and a device for communicating therebetween. Included is a first serial advanced technology attachment (SATA) port, a second SATA port, and a third SATA port. The first SATA port includes a first host task file coupled to a first host unit, and the first host task file is responsive to commands sent by the first host unit to the device. The second SATA port includes a second host task file coupled to a second host unit, and the second host task file is responsive to commands sent by the second host unit to the device. An arbitration control circuit is coupled to the SATA ports, and selects from the first and second hosts to concurrently access the device, through the switch, accepting commands from either host units at any time, including when the device is not idle.

Abstract: A switch is coupled between a plurality of host units and a device, for communicating therebetween. A first serial advanced technology attachment (SATA) port includes a first host task file, and is coupled to a first host unit. A second SATA port includes a second host task file, and is coupled to a second host unit. The task files are responsive to commands sent by the respective host units, and cause access to the device by the host respective host units. A third parallel ATA port includes a device task file, and is coupled to a device, for access to the device by the first or second host units. An arbitration and control circuit is coupled to the task files, for selecting one of the first or second host units to concurrently access the device through the switch at any given time, including when the device is not idle.

Abstract: A communication system is disclosed in one embodiment of the present invention to include an encoder circuit responsive to an audio signal for performing compression on the audio signal and adaptive to generate an audio output signal based upon the compressed audio signal, the encoder circuit for sampling the audio signal to generated sampled signals, each sampled signals having a real and an imaginary component associated therewith, each sampled signal having an energy and a phase defined within a current block and each sampled signal being transformed to have a real and an imaginary component, a previous block preceding the current block and a block preceding the previous block, the encoder circuit for calculating the phase of the samples of the current block using the real and the imaginary components of the samples of the previous block and the block preceding the previous block, wherein calculations for determining the unpredictability measure is reduced by avoiding trigonometric calculations of the samp

Abstract: Defect management for automatic track processing without an ID field, processes defect information for a track on a magnetic media within a disk drive system. A system which uses any method of defect management including linear replacement, sector slipping, cylinder slipping or segment slipping, can be supported. A physical sector number for each sector is translated to a logical sector number relating to the order of data on a track. This translation of the physical sector number to a logical sector number for automatic track processing can be accomplished using any one of three methods: 1) a track defect table can be built in the buffer RAM; 2) the defect information can be written in the header of every sector; or 3) a system FIFO, located in the onboard logic, can be used to manage the defect list. In the second method, the header subfield comprises four defect records.

Abstract: An embodiment of the present invention is disclosed to include a nonvolatile memory system for controlling erase operations performed on a nonvolatile memory array comprised of rows and columns, the nonvolatile memory array stores digital information organized into blocks with each block having one or more sectors of information and each sector having a user data field and an extension field and each sector stored within a row of the memory array. A controller circuit is coupled to a host circuit and is operative to perform erase operations on the nonvolatile memory array, the controller circuit erases an identified sector of information having a particular user data field and a particular extension field wherein the particular user field and the particular extension field are caused to be erased separately.

Abstract: A preferred embodiment of the present invention is disclosed to include a router system having a trunk feature card and at least one modem feature card for transferring communication information between the modem feature cards through a TDM backplane, to the trunk card, for transfer thereof to Digital Subscriber (DS) lines, the router and modem cards while co-existing within the same router system, having no knowledge of the characteristics of each other with many different combinations of such trunk and modem cards being employed by the router system. The router system accommodating “over-subscription” situations wherein the number of DS lines is less than the number of modems and initialization the system such as to maximize the utility of the DS lines as a function of the type of modem cards in the system.

Abstract: In a digital system having a host, a controller device and at least one flash memory integrated circuit, a method and apparatus for storing location identification information regarding blocks of information within at least one of the flash memory integrated circuits wherein at least two buffers within the at least one of the flash memory integrated circuits are designated as primary and secondary buffers for storing the identification information in the primary buffer until the primary buffer is effectively full and storing additional identification information in the secondary buffer until it is effectively full, swapping buffer designation so that the primary buffer becomes the secondary buffer and the secondary buffer becomes the primary buffer, erasing the effectively-full buffer for re-use and in this manner, continuously swapping storage of identification information between the two buffers.

Abstract: A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an "original" location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a "moved" location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the "original" physical block address and the "moved" physical block address and for providing information regarding "moved" sectors within the block being accessed.

Abstract: In accordance with an embodiment of the present invention, a solid state storage system and method is disclosed for reducing the number of write operations when re-writing a block of information that has been previously written by a host. The system includes a controller coupled to a host and a nonvolatile memory unit for controlling reading and writing of information organized in sectors from and to the nonvolatile memory unit, as commanded by the host. The controller maintains mapping of the sector information in an LUT stored in volatile memory the contents of which are lost if power is lost. Through the use of an address value and flag information maintained within each of the blocks of the nonvolatile memory unit, a block is re-written using a different number of write operations in various alternative embodiments of the present invention.

Abstract: The present invention includes a digital system having a controller semiconductor device coupled to a host and a nonvolatile memory bank including a plurality of nonvolatile memory devices. The controller transfers information, organized in sectors, with each sector including a user data portion and an overhead portion, between the host and the nonvolatile memory bank and stores and reads two bytes of information relating to the same sector simultaneously within two nonvolatile memory devices. Each nonvolatile memory device is defined by a row of memory locations wherein corresponding rows of at least two semiconductor devices maintain two sectors of information therein with the overhead information relating to the two sectors maintained in one of the memory rows of the nonvolatile memory device.

Abstract: In accordance with an embodiment of the present invention, a controller device is disclosed for use in a digital system having a host and nonvolatile memory devices. The controller device is coupled to the host and at least two nonvolatile memory devices. The host stores digital information in the nonvolatile memory unit and reads the stored digital information from the nonvolatile memory unit under the direction of the controller, the memory unit being organized into blocks of sectors of information. The controller device erases the digital information stored in the blocks of the nonvolatile memory devices in-parallel form. The controller device includes a space manager circuit responsive to address information from the host and operative to read, write or erase information in the nonvolatile memory unit based upon the host address information.

Abstract: The present invention includes a circuit for deriving a reference signal having a reference voltage from a system voltage source having a system voltage level and for regulating the reference voltage level. The circuit includes an output sub-circuit, a reference generator sub-circuit, a regulator sub-circuit, a translator sub-circuit, and a low pass filter sub-circuit. The output sub-circuit, which is coupled to the system voltage source, is responsive to a voltage control signal, and is operative to generate the reference signal wherein the reference voltage level is less than or equal to the system voltage level. The reference generator sub-circuit is responsive to the reference signal and is operative to generate a prime voltage level which remains substantially unaffected by fabrication process variations, temperature variations and variations in the reference signal.

Abstract: In a digital system having a host, a controller device and at least one nonvolatile memory integrated circuit, such as a flash memory chip, a method and apparatus is disclosed for storing digital information, provided by the host, in the nonvolatile memory under the direction of the controller in an efficient manner so as to significantly improve system performance. The nonvolatile memory is organized into sequentially-numbered blocks. Each nonvolatile integrated circuit is assigned a predetermined number of sequential blocks and when a free block is solicited for storage of digital information provided by the host, the nonvolatile integrated circuit rather than the entire nonvolatile memory is searched for the free block. When the information stored in a block is being updated by the host, the nonvolatile integrated circuit assigned to that block is excluded from the search for the free block.