Abstract: In a digital system having non-volatile memory devices for storage of digital information therein, the digital information being organized in sectors, each sector having a data field and a corresponding extension field, a controller device for performing operations such as reading and writing to and erasing information from a selected plurality of sectors and further verifying successful erasure of the selected erased sectors, the controller device including an error detection circuit for detecting errors within each of the sector data fields using the corresponding sector extension field and a flash interface circuit coupled to the non-volatile devices through a data bus for receiving an erased sector of information therethrough and being operative to pass the data field of the erased sector information and a predetermined extension field to the error detection circuit wherein the error detection circuit calculates an extension field corresponding to the erased sector data field, compares the calculated exte

Abstract: A method and apparatus is disclosed for increasing the system performance of a digital system having a controller for controlling nonvolatile devices for storing blocks of information, each block having a group of sectors. When sectors within a block are being re-written in sequential order, the controller writes the new sector information into a sector location of another block without the need to move any of the sectors within the original block thereby reducing the number of read and write cycles needed to avoid erase-before-write operations. A `used` flag, stored in the sector location of each block, indicates that the sector has been transferred to another block or, alternatively, a move locator word maintains status information regarding the position of the sectors within the block that have been moved.

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid an erase cycle each time information stored in the mass storage is changed. Erase cycles are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically the mass storage will need to be cleaned up. These advantages are achieved through the use of several flag, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block. An array of volatile memory is addressable according to the logical address and stores the physical address.

Abstract: A device is disclosed for storing mapping information for mapping a logical block address identifying a block being accessed by a host to a physical block address, identifying a free area of nonvolatile memory, the block being selectively erasable and having one or more sectors that may be individually moved. The mapping information including a virtual physical block address for identifying an "original" location, within the nonvolatile memory, wherein a block is stored and a moved virtual physical block address for identifying a "moved" location, within the nonvolatile memory, wherein one or more sectors of the stored block are moved. The mapping information further including status information for use of the "original" physical block address and the "moved" physical block address and for providing information regarding "moved" sectors within the block being accessed.

Abstract: In storage subsystems such as winchester disk, blocks of sequential data corresponding to sectors are concurrently accessed by the disk and the host. Semiconductor memory devices for storing block data are often utilized as storage location for sectors of data read or written to the disk and the host. Application of a semiconductor memory which increases the effective transfer rate of the system is highly desirable particularly in disk storage systems. A semiconductor memory for use in disk storage applications where information is transferred in blocks of data is hereby disclosed. Specifically, the memory includes a main memory configured as a random access memory array having rows and columns, each row having a plurality of n-bit words, a secondary memory having a data register file, first and second parallel-by-bit interfaces and a transferring circuit for transferring data between the main and secondary memories.

Abstract: A microcontroller down-loadable memory organization supporting "shadow" personality, optimized for connecting a computer system to an ISDN network to facilitate transmitting and receiving of data, the microcontroller including a processor and a memory structure having ROM memory space for storing program code therein and further including a dual port RAM for connection between the computer and the processor, the dual port RAM having RAM memory space for storing program code therein and shared RAM for storing data capable of being simultaneously accessible by the processor and the computer, wherein the program ROM and the program RAM are selectively used by the computer to store program code by the computer using a ROM/RAM* select signal, and wherein the starting address in the shared RAM wherein data is stored is selectably offset from the starting address of the code RAM and the code ROM.

Abstract: A nonvolatile semiconductor mass storage system and architecture can be substituted for a rotating hard disk. The system and architecture avoid erase cycles each time information stored in the mass storage is changed. Erase cycle are avoided by programming an altered data file into an empty mass storage block rather than over itself as a hard disk would. Periodically, the mass storage will need to be cleaned up. These advantages are achieved through the use of several flags, and a map to correlate a logical block address of a block to a physical address of that block. In particular, flags are provided for defective blocks, used blocks, and old versions of a block.

Abstract: A method and apparatus is disclosed for identifying a block being stored within flash memory devices using a cluster address for each block, the block being selectively erasable and having one or more sectors, the cluster address being stored in one of the sectors of the block. In an alternative embodiment, the cluster address is stored in at least two different sectors within the same block for ensuring that the information last written to the block is valid. Further disclosed is a novel way to use a defect flag for each block stored within the flash memory device for efficiently identifying non-defective blocks upon system power-up.

Abstract: A semiconductor non-volatile mass storage memory is partitioned into user files and system files. The system files partition is further subdivided into clusters, each cluster having a plurality of sectors. Each cluster stores the system file for a single predetermined LBA. As the information within the LBA is changed, the new information is written into an empty sector within the cluster. Once the cluster is filled, the system either erases for recycling the cluster or preferably locates an empty cluster and repeats the process with that new cluster. Once all the clusters are filled, all clusters containing old data are erased for recycling.

Abstract: A circuit is provided for selecting one of plurality of integrated circuit chips with a minimum number of chip select signal lines. A first embodiment includes a plurality of paired address lines; each line in each pair provides a logical complementary signal. Only a selected one of the lines of each pair is coupled to integrated circuit. Each of the integrated circuits is coupled to a unique combination of these selected lines of the pairs. In a second embodiment a select signal is clocked by a controller from one of the integrated circuits to the next in a fashion similar to a shift register. Once the select signal is present in the desired integrated circuit, the controller then provides an enable signal to all the integrated circuits which enables only that desired integrated circuit. In yet another embodiment, the address lines are also used a chip select signal lines, one address line for each integrated circuit. A Chip.sub.-- select.sub.-- clock.sub.

Abstract: A computer card including a voltage detection circuit having Flash EEPROM devices and a controller device, the voltage detection circuit further including a variable voltage detector for determining the system voltage level provided by a power supply within the computer product and appropriately enabling a voltage regulator circuit for dividing the system voltage level to a level suited for operation by the Flash EEPROM devices and applying this operational voltage level to the Flash EEPROM devices. Upon determining the system voltage level provided by the power supply to be appropriately suited for operation of the Flash EEPROM devices, disabling the voltage regulator circuit and providing the system voltage level to the Flash EEPROM devices.

Abstract: A remote communication system for facilitating secure electronic sales of products, wherein a suitable seller input device in association with a local seller data transmission system couples the seller to a packet network system for communicating to a remote receiver/decoder apparatus to download registration data to the seller system. Upon retrieving a telephone toll number from the remote apparatus, a telcom network communication link for communicating the telephone number from the seller to the remote receiver allows the seller to upload the product that is to be offered for sale to the remote apparatus. The telcom connection, linking the seller system to the remote apparatus may also include a 900 number billing system whereby a fee is assessed and charged at a rate determined by the toll connection provider after uploading the product.

Abstract: A table driven method and apparatus for automatic split field processing in a disk drive system stores data representing the split fields after each servo mark of a frame. Each track of the disk drive system is divided up into frames or groups of sectors or equivalently servo marks, each frame comprising a predetermined number N of sectors and a predetermined number M of servo marks. Beginning from the INDEX mark, after every N sectors or equivalently M servo marks, the next sector must start after the next servo mark. The value N is a constant within each zone on a disk but can vary from zone to zone as the storage density changes. The information for each servo mark within a frame is stored in a frame table in the buffer memory. A starting address pointer and an ending address pointer are used to keep track of the starting and ending addresses, respectively, of the frame table. An address pointer is used to point to the current entry of interest in the frame table.

Abstract: A microprocessor-controlled solid state storage system having a controller and non-volatile memory for storing firmware code therein. The controller includes first memory for storing firmware code transferred from the non-volatile memory, and second memory including primitive firmware code stored therein causing execution of a microprocessor for transferring the firmware code from reserved blocks in the non-volatile memory into the first memory upon initialization of the storage system and causing calculation of a checksum for verification of the integrity of the firmware code.

Abstract: A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

Abstract: A semiconductor memory device is disclosed including a main memory configured as a dynamic random access memory array having rows and columns, combined with a secondary memory having a data register file, a transferring circuit for allowing transfer of data between the main memory and secondary memory, a first parallel-by-bit interface for random accesses to the main memory and a second parallel-by-bit interface for access to the seconday memory. Concurrent and independent accesses of the main and secondary memories is achieved while maintaining the integrity of data. Further included in the secondary memory is a data register file and a corresponding mask register file wherein the latter achieves selection of any combination of words in a row of the secondary memory for the purposes of transferring the same to the main memory.