Abstract: An information technology system includes a micro projector display for displaying status, operating, troubleshooting, and location information. An image output from the micro projector display is viewable from outside the enclosure, for example on a cabinet door, an optional retractable projection screen included with the enclosure, or a floor, wall, or ceiling of a room, or other external surface. In some embodiments of the invention, a micro display projector is adapted for removable electrical and mechanical connection to one or more docking ports on the information technology system. In some embodiments of the invention, a projection direction for the micro projector display is selectable.

Abstract: A permute unit includes permute logic and a crossbar working in cycles defined by clocking signals and generates one valid output vector per cycle by treating two parallel input vectors per cycle. The permute unit is double pumped by performing two inner cycles per outer cycle defined by the clocking signals. In the first inner cycle, first halves of both input vectors are treated. In the second inner cycle, second halves of both input vectors are treated and a valid output vector is generated from the results of the treatments within the first and the second inner cycles.

Abstract: Methods and a computer program product related to the management of possibly logically bad blocks in storage devices are disclosed. A logically bad pattern is placed in a standard size data block if data associated with the data block has previously been stored or is waiting to be stored, but has subsequently become lost. The logical block address associated with the data block is stored in a bad block table. The possibly logically bad pattern is able to be detected, and the bad block table is checked to determine if the data block to be read is in fact Logically Bad. A data check response may be given if the logical block address is present in a Bad Block Table. The possibly logically bad pattern may have a first predefined data portion and a second predefined data portion and may be repeated to fill the standard size data block.

Abstract: A power regulation scheme includes a first voltage regulation portion connected in parallel with a second voltage regulation portion that regulates a voltage if an open condition occurs within the first voltage regulation portion. Each voltage regulation portion may include a first voltage regulator connected in series with a second voltage regulator that regulates the voltage if a short condition occurs within the first voltage regulator. Each voltage regulation portion may utilize a switching element to route an output voltage of the first voltage regulator past the second voltage regulator if the output voltage has been regulated and/or to force the output voltage to be regulated by the second voltage regulator if the output voltage has not been regulated.

Abstract: A method of statistical analysis is based on an accelerated degradation model for estimating the failure rate from a set of accelerated life data (e.g. stress, humidity, temperature, voltage, resistance, vibration, etc.). The method re-samples randomly distributed data and organizes it into subsets that may be ordered. The maximum is found for each subset. From the maximums a parametric LEV distribution is determined. Maximum Likelihood Estimation methods may be used to find the parameters employed in the determined LEV distribution. The failure rate is calculated using the determined LEV distribution of the sample maximums.

Abstract: For example, a method of detecting frame marker quality includes: detecting, in a bit-stream sent from a first component to a second component of a common hardware unit, a frame marker having a bit pattern different from an uncorrupted frame marker specified by a communication protocol; and assigning a quality level indicator to the frame marker based on a difference between said bit pattern and a bit pattern of said uncorrupted frame marker.

Abstract: A design structure embodied in a machine readable storage medium designing, manufacturing, and/or testing a design that includes a multi-threaded processor that executes an instruction of a process of an executing program is provided. The multi-threaded processor includes at least a first and a second thread. First and second sets of source registers are respectively allocated to the first and second threads, and first and second sets of destination registers are respectively allocated to the first and second threads. A resource prefix configuration register includes mappings between each of the source and destination registers and the threads. The multi-threaded processor, during execution of the instruction by one of the first or the second threads of execution, accesses the source and destination registers based on the mapping, wherein at least one of the accessed registers is allocated to the other of the first or the second thread of execution.

Abstract: Memory is logically partitioned into two regions. A first region may be a similar size relative to the second region or the first region may be a small subset of the memory. The first region of memory is initialized and an operating system utilizes the first region. A system handler simulates a physical hot add of the second region. After the simulated physical hot add, the operating system may utilize the second region as if it were newly added physical memory and/or may utilize both the first region and second region.

Abstract: A video stream encoding apparatus and method therefore is herein described. The video stream encoding apparatus includes a divider for dividing a frame in a video stream into a plurality of processing units, each processing unit including a plurality of macro-blocks; and an encoder for encoding the plurality of macro-blocks in each processing unit in parallel. The same quantization parameters are used for respective macro-blocks in the same processing unit in the quantization of the encoder. By the apparatus and the method of the invention, dependencies between macro-blocks are broken, and the precision of high rate controlling is kept while encoding the respective macro-blocks in parallel.

Abstract: A memory system and methods for memory manage are presented. The memory system includes a volatile memory electrically connected to a high-density memory; a memory controller that expects data to be written or read to or from the memory system at a bandwidth and a latency associated with the volatile memory; a directory within the volatile memory that associates a volatile memory address with data stored in the high-density memory; and redundant storage in the high-density memory that stores a copy of the association between the volatile memory address and the data stored in the high-density memory. The methods for memory management allow writing to and reading from the memory system using a first memory read/write interface (e.g. DRAM interface, etc.), though data is stored in a device of a different memory type (e.g. FLASH, etc.).

Abstract: In various embodiments a traffic class manager is a resource within a virtualized computer systems trusted entity (i.e. a hypervisor, trusted partition, etc.) which maps requirements from a platform management and associated network capabilities onto an SR-IOV adapter in order to appropriately allocate SR-IOV adapter and network resources to the virtualized computer partitions. In various embodiments the traffic class manager defines network traffic classes that meet the objectives of a platform administrator based on the capabilities of the SR-IOV adapter and the network attached to the adapter ports. Once the traffic classes are defined, in various embodiments, the traffic class manager enforces the assignment of a traffic class to a virtual interface queue pair within a partition.

Abstract: Detect four sets of first touch coordinates (A, B, C, D) on a touch panel. Divide an area delimited by the detected four sets into two areas of triangles (ABD, BCD). For each area of triangle, obtain a first correction factor. Detect a set of second touch coordinates (P, Q) selected within a respective one of the areas of triangles. Convert the detected set of second touch coordinates into a set of first corrected coordinates. Detect a difference between the set of first corrected coordinates and a set of true display coordinates. Where the detected difference is greater than a predetermined threshold value, further divide the area of triangle (BCD) into three areas of triangles (QBD, QBC, QCD). Obtain a second correction factor using the set of second touch coordinates and the sets of first touch coordinates corresponding to the vertices.

Abstract: Read commands on a mirrored memory computer system are scheduled by utilizing information about pending memory access requests. A conflict queue is configured to track a read/write queue associated with each of a plurality of memory ports on the mirrored memory system. The conflict queue determines a predicted latency on each memory port based on the contents of each of the read/write queues. A compare logic unit is coupled to the conflict queue, wherein the compare logic unit compares a predicted latency of a primary memory and a mirrored memory and schedules read commands to the memory port with the lowest predicted latency.

Abstract: The present invention relates to method and system for accessing a resource implemented in a computer network, wherein a plurality of different runtime environments exist used by either one of the resources or by a systems management application accessing one of the resources, wherein the different runtime environments require the usage of a web service resource framework comprising a plurality of respective different, runtime-specific web service standards.

Abstract: A first through via is electrically insulated from surrounding wafer substrate material. A second through via is not electrically insulated from the surrounding wafer substrate material. This configuration is advantageous when the non-insulated via serves as the path for either Vdd or GND. By not insulating the through via, a first supply voltage (Vdd or GND) is allowed to flow through the surrounding wafer substrate material thereby decreasing the resistance of the first supply voltage path.

Abstract: A method of configuring a software product comprises accessing a user model, the user model defining one or more user roles and one or more tasks, each task linked to a role, accessing a task to software function map, the map defining one or more software functions of the software product and one or more tasks, each software function linked to a task, and configuring the software product so that access to the software product according to a specific user role is via a user interface supporting the software functions linked to the specific role via the tasks.

Abstract: In response to a hypervisor page fault for memory that is not resident in a shared memory pool, an I/O paging request is sent to an external storage paging space. In response to a paging service partition encountering an I/O paging error, a paging failure indication is sent to the hypervisor. A simulated machine check interrupt instruction is sent from the hypervisor to the shared memory partition and a machine check handler obtains control. The machine check handler performs data analysis utilizing an error log in an attempt to isolate the I/O paging error to a process or a set of processes in the shared memory partition. The process or set of processes associated with the I/O paging error, or the shared memory partition itself, may be terminated. Finally, the shared memory partition may clear or initialize the page associated with the I/O paging error.

Abstract: A power regulation circuit includes at least a first regulator connected to a second regulator in series forming a first regulator pair and a third regulator connected to a fourth regulator in series forming a second regulator pair. The first regulator pair is connected in parallel with the second regulator pair. Each individual regulator is configured to separately regulate an input voltage to a predetermined regulated output voltage. The second regulator pair regulates the input voltage if a short condition occurs within the first regulator pair and the second and fourth regulators each regulate the input voltage if an open condition occurs within the first or third regulator respectively.

Abstract: This invention generally provides a method for speeding up system boot time, by initializing a subset of memory during the system firmware test/initialization, and allowing the system to boot an operating system with this subset of installed memory. While the system is completing the operating system boot with the subset of installed memory, a remainder of the installed system memory is being initialized/tested. When the initialization the remainder of system memory is completed (and after the OS has booted), the SMI handler is invoked. The SMI handler then simulates a physical memory “Hot Add” event, and reports the event to the OS. This allows much of the memory initialization/test activity to occur in parallel with the firmware initialization/test and operating system startup processes.

Abstract: A heat exchange system for blade server systems is disclosed, wherein said blade server system contains a plurality of server blades arranged in a blade center, wherein the heat exchange system comprises first heat sink associated to each of said plurality of server blades, and whereby the first heat sink are adapted to collect heat emitted from heat emitting devices on said associated server blade; means for transferring heat from the heat emitting devices to the first heat sink; and a liquid cooled second heat sink associated to said blade center, whereby said first heat sink are connected to said second heat sink by thermal coupling.