Abstract: The present invention comprises a method and apparatus for an integrated circuit (IC) that uses 1 of N signals to reduce the circuit's wire to wire effective capacitance. The present invention comprises a logic tree circuit coupled to a first 1 of N input signal, a second 1 of N input signal, and a 1 of N output signal where the 1 of N signals' reduce the signal's wire to wire effective capacitance. Other embodiments of the present invention include the use of a 1 of 2 signal, a 1 of 3 signal, a 1 of 4 signal, and a 1 of 8 signal where one and one of the wires of the signal is active.

Abstract: A beam of accelerated ions (111) is produced from a quiescent plasma (19) created by diffusing a heated primary plasma (15) through an accelerator/homogenizer structure (17) having a uniform voltage potential VB and a total surface area ARF. The RF-conductive, dielectric coated surfaces of the accelerator/homogenizer structure are quasi-uniformly dispersed throughout the primary plasma. The quiescent plasma has a generally homogenous preselected plasma potential VPA approximately equal to VB. An RF-grounded structure (112) having a total ground surface area AG, wherein ARF>AG, attracts ions from the quiescent plasma to produce the accelerated ion beam.

Abstract: The generic protocol translator enables a robust communication link between devices where communication and the exchange of information is currently either very difficult or impossible. The generic protocol translator frees device developers from concerning themselves with the details of existing and future protocols, data formats or application semantics that they must support for inter-device compatibility. A receiver circuit manager receives source information using a socket-type interface. The source information then passes through a receiver, a message queue, a message router, and a message converter, which converts the information to the destination format using a multi-stage pipelined poly-dimensional finite state automata based conversion process. The converted message is then sent to the destination device via the message router after being reformatted into the destination protocol identified during the conversion process.

Abstract: A system resource router interfaces initiators through protocol-adapting sockets to a plurality of sub-buses. A switch matrix allows at least some of the sockets to be connected to two or more of the sub-buses. Each sub-bus interfaces through a channel controller to target devices like memory and peripherals. A graphical user interface, assembly program, and computer-aided design platform allow users to customize system resource router configurations for particular applications. At least one embodiment produces Verilog or other hardware description language intellectual property technology libraries. It implements the optimal mix of sub-buses, switches, sockets, and controllers that will be needed for a particular user application.

Abstract: A method and apparatus for random-access scan of a network 990 of dynamic logic or N-NARY logic that includes sequentially clocked precharge logic gates and one or more scan gates (900) driven by multiple overlapping clock signals generated from a clock generation circuit (904) coupled to a clock spine (902). Each clocked precharge logic gate and each scan gate include a logic tree (502) with one or more evaluate nodes, a precharge circuit (32), an evaluate circuit (36), and one or more output buffers (34). Each scan gate further includes a scan circuit (806) that accepts scan control signals (406, 408, 410, 824, and 826) and couples to one or more scan registers (416) in a RAM-like architecture. Scan control signals operate to capture the state of the output buffers of the scan gate, and to force the output buffers of the scan gate to a preselected level.

Abstract: This invention discloses a software tool 20 that generates wire route rules between logic gates in a semiconductor device for the automated layout of the logic gates in the device. The software tool 20 includes a routing rule generation tool 22 that creates a route rule database 30 for a given semiconductor fabrication technology and circuit family of logic gates, and includes a block build tool 32 that interconnects the logic gates with routes according to the route rules generated by the routing rule generation tool 22. The routing rule generation tool 22 further includes a noise sensitivity/gate characterization tool 24 and a rule generator tool 28. The block build tool 32 further includes a gate sizing tool 34, a gate analysis tool 36, a route rule selecting tool 38, a route assigning tool 42.

Abstract: A random number indexing method and apparatus includes an index array 302 that uniquely identifies each pseudo-random number in a sequence of numbers generated by a pseudo-random number generator 202. A computer program 102 provides a seed value to the pseudo-random number generator and populates the index array. The computer program uses the identifying indicia in the index array to call for and receive pseudo-random numbers.

Abstract: A static output signal is generated using a static storage element (104) and transmitted to a NDL gate (110) over a transmission path (112) that is characterized by a user-specified multi-cycle timing constraint that is used to create appropriate verification tests of the apparatus. The multi-cycle timing constraint may be a pragma that is interpreted by the compiler of a timing analysis tool such as PATHMILL to automatically check the set-up and hold times of the static signal relative to the rising edge or falling edge of user-specified clock signal pulses. The same pragma is interpreted by the compiler of a functional verification tools such as VIS to create statements that test the behavior of the apparatus during the clock signal pulses other than the user-specified clock signal pulses tested by the timing analysis tool.

Abstract: A method and apparatus that minimizes instruction gaps behind a branch instruction in a multistage pipelined processor is disclosed. A pre-branch instruction that corresponds to a branch instruction to inserted into the instruction stream a sufficient number of instructions ahead of the branch instruction to insure that the pre-branch instruction exits the decode stage of the pipeline at the same time the branch instruction exits the first instruction fetch stage of the pipeline. The pre-branch instruction is decoded and causes the instruction fetch unit either to begin fetching instructions at a target address, where the branch is known or predicted to be taken, or to continue fetching instructions along the main execution path, the branch is known or predicted to be not taken.

Abstract: A method of efficiently simulating logic designs comprising signals that are capable of having more than two unique decimal values and one or more unique drive states, such as designs based upon the new N-nary logic design style, is disclosed. The present invention includes a signal model that models N-nary signal value, drive strength, and signal definition information in a specific format that supports the ability of the simulator to simulate the operation of the N-nary logic gates such as adders, buffers, and multiplexers by arithmetically and logically manipulating the unique decimal values of the N-nary signals. The simulator comprises an input logic signal model reader, an arithmetic/logical operator, an output logic signal model generator, and an output message generator that generates one or more output- or input-signal-specific output messages that pack relevant simulation data into a format optimized to the architecture of the simulation host.

Abstract: A system-on-chip interconnection structure and method uses unidirectional buses only, central shared memory controllers, separate interconnects for high-speed and low-speed peripherals, zero wait-state register accesses, application-specific memory map and peripherals, application-specific test methodology, allowances for cache controllers, and good fits with standard ASIC flow and tools.

Abstract: The present invention is a grid that is a monitor that detects a cross product of design verification events and reports a single status event to a database. One embodiment of the present invention comprises axes declarations, logic expressions, and a grid declaration. An axes declaration produces a cross product of verification events. A logic expressions evaluates whether a specific verification event has occurred. A grid declaration returns the status event. The present invention further comprises a grid where the cross-product of verification events comprises a fully or a sparsely populated cross-product of verification events. Additionally, the present invention further comprises a grid that uses N-Nary signals. And, the present invention comprises a parser to translate the monitor source file code into a standard computer language code.

Abstract: A logic device with improved capacitance isolation and a design methodology that reduces parasitic capacitance is disclosed. The logic device includes a virtual ground node, a plurality of input signals that may be individual wires of one or more N-NARY signals, and two or more discharge paths. Each discharge path includes an evaluate node, one or more transistors gated by the input signals, and one or more intermediate nodes, one of which is coupled to the virtual ground node. In one embodiment, the discharge paths are perfectly isolated from each other for every combination of inputs. In another embodiment, intermediate nodes on discharge paths maybe electrically coupled to the evaluation path only at the intermediate node coupled to the virtual ground node.

Abstract: The present invention is a 5:2 carry-save-adder (CSA) that receives the five input signals I0, I1, I2, I3 and I4 and computes the two output signals SUM and CARRY. The 5:2 CSA comprises a first level of logic circuitry and a second level of logic circuitry. The first level of logic circuitry comprises a plurality of adders and receives the input signals and generates three intermediate terms T0, T1, and T2. The second level of logic circuitry comprises a carry logic circuit and a sum adder, and uses the intermediate terms to compute the two output signals SUM and CARRY. The 5:2 CSA of the present invention operates using either binary signals or N-NARY signals.

Abstract: A method and apparatus that performs anticipatory rounding of intermediate results in a floating point arithmetic system while the intermediate results are being normalized is disclosed. One embodiment of the present invention includes four logic levels, implemented in N-NARY logic. In the first three logic levels, propagation information is gathered for preselected bit groups from the coarse and medium shift output of the normalizer as those results become available. In the fourth level, an incremented, normalized intermediate single-precision or double-precision mantissa result is produced by combining fine shift output bit values with propagation information for the appropriate top bit group, middle bit group, and bottom bit group. The appropriate bit groups are determined by examining the value of the fine shift select signal.

Abstract: The RF-powered plasma accelerator/homogenizer produces a quiescent plasma having a generally homogenous preselected plasma potential VPA and a space-charge neutralized plasma beam. The plasma accelerator/homogenizer includes an RF-conductive accelerator/homogenizer structure (17) having a plurality of dielectric-coated accelerator/homogenizer surfaces (619) with total surface area ARF and a containment assembly that includes an RF-grounded structure (112) with a total ground surface area AG, where ARF>AG. The accelerator/homogenizer structure is reactively coupled to an RF source using various approaches for direct or stray capacitive coupling (16).

Abstract: An efficient leading zero/leading one anticipator (LZA) that can operate in parallel with a floating point adder is disclosed. In one embodiment, the LZA can be implemented in three levels of N-NARY logic, wherein the first logic level generates dit-level propagate-generate-zero (PGZ) patterns and carry out signals from the input dits of the adder operands. The second logic level produces a find-zero and a find-one output signal for each two-dit group of the adder result by combining PGZ patterns for the two dits within the group with the carry-out signal from the dit immediately preceding the two-dit group. The third logic level combines find-zero and find-one output signals for each two-dit group to produce find-one and find-zero coarse and medium shift select signals.

Abstract: The present invention comprises a method and apparatus for a pipeline of functional units with a late pipe functional unit that executes instructions without stalling until the result is available. The present invention comprises one or more earlier functional units coupled to a late pipe functional unit. The late pipe functional unit does not begin executing instructions until all of the input operands are or will be available for execution so that the late pipe functional unit will execute instructions without stalling until the result will be available in a fixed number of cycles. The present invention further comprises a late pipe functional unit that may comprise a floating point unit, a graphics unit, or an enhanced floating point unit. And finally, the late pipe functional unit is non-stalling and or is non-cancelable.

Abstract: The present invention is a method and apparatus for building a software system in a networked software development environment, utilizing existing software version control and build tools such as RCS and MAKE. Source and object files are loaded into network caches shared by multiple users at local workstations. At individual workstations, a cache link structure generated from a user-created build list is provided to the software building program, which then builds the desired software system using links to cached files. The present invention thus minimizes the amount of computing resources required to build software programs by eliminating the need to store multiple local copies of building block software files, and to rebuild object files that may be unchanged from prior builds. A method for maintaining and updating network caches to maximize the efficiency of cache link creation is also disclosed.

Abstract: The present invention is a dynamic logic propagation delay targeting tool that includes a gate target delay initializer 90, a levelizer 82, a backward logic scanner 94, a forward logic scanner 96, a gate target delay incrementor 97, and a gate target delay comparator 97 that together calculates the propagation delay of a signal in a specified block of dynamic logic.