Abstract: The voltage regulator circuit includes a Darlington pass device, a feedback circuit and an error amplifier connected between the feedback circuit and the Darlington pass device. The error amplifier is arranged to conduct a current which is proportional to the control current of the pass device so that under standby conditions when the control current of the pass device has a low magnitude the power dissipation of the voltage regulator is minimized. A high voltage sustaining transistor, which is connected between the pass device and the error amplifier, is arranged to have a high voltage sustaining capability.

Abstract: Combining integrated injection logic (I.sup.2 L) and linear circuitry permits fabrication of a highly dense analog-to-digital (A-to-D) converter. The heart of the A-to-D converter is a linear-I.sup.2 L plurality of high density variable current sources which are proportional to each other. These variable current sources, when used in combination with I.sup.2 L constant current sources and current sensing means, provide a highly compact A-to-D converter.

Abstract: A current supply circuit is disclosed having a field effect transistor and negative feedback for degenerating the magnitude of the current supplied thereby. The negative feedback can be provided by a diffused resistor connected between the gate and source electrodes of the current supply field effect transistor. A differential amplifier which includes a pair of differentially coupled amplifying field effect transistors is coupled to the current supply circuit. The negative feedback enables the current supply device to provide a current which compensates the differentially coupled field effect transistors over processing while not deleteriously affecting the temperature characteristics thereof. A bipolar diode and a bipolar transistor can be included in the current supply for enabling the resistor to take up less chip area and for allowing more flexibility in the design of the geometry of the current supply, field effect transistor.

Abstract: A clamp circuit is disclosed which includes a transistor connected between the multiple collectors of a bias current device for complementary output transistors and the output terminal of a driver circuit. The clamp transistor is rendered conductive by signals at the output terminal of the driver circuit which would otherwise heavily saturate the bias current device. The clamp transistor conducts current to provide additional needed bias to the complementary output device and to keep such current from disturbing the magnitudes of currents provided by a current generator circuit which is also connected to the bias current device.

Abstract: A "D" flip-flop circuit is disclosed which includes a master latch having data input transistors coupled to the input terminals thereof and data transfer transistors connected to the output thereof. A slave latch is connected to the output terminals of the data transfer transistors. The flip-flop circuit utilizes a resistive feedback network coupled between the emitter terminals of the transistors of the master latch to facilitate increased output voltages and stable predictable operating conditions. The data input transistors are connected as emitter follower circuits for driving the master latch transistors in a common base configuration for maximizing the speed-power product of the circuit.

Abstract: A circuit for providing a control signal having a first predetermined magnitude in response to an analog voltage having a magnitude below a particular threshold and the control signal having a second predetermined magnitude in response to the magnitude of the analog voltage being above the particular threshold includes a threshold establishing circuit, a first transistor and a second transistor. The threshold establishing circuit receives the analog voltage and enables the first transistor to remain non-conductive until the analog voltage reaches the threshold. The second transistor is connected to the first transistor and to the analog voltage supply. The second transistor is arranged to be initially conductive as the magnitude of the analog voltage rises, and to become non-conductive in response to the first transistor being rendered conductive so that the desired control signal is developed at an output electrode of the second transistor.

Abstract: A doppler range detector with early and late range gates responding to radar returns or either side of maximum velocity range and supplying a peak output amplitude when the early and late gates have the same doppler frequency. A peak detector is used to detect slant range with a dual pulse ranging system. The returns are supplied to two zero beat mixers, the output signals of which are passed through separate bandpass filters to a multiplier. The multiplier output is supplied through a low pass filter to the peak detector.

Abstract: The disclosed amplifier includes first and second gain stages and first and second frequency compensating capacitors. The second gain stage has a first high impedance node coupled to the first gain stage, a second high impedance node, a first circuit coupled between the first and second high impedance nodes, a third high impedance node, and a second circuit coupled between the second and third high impedance nodes. The impedances at the first, second and third high impedance nodes are a function of frequency and the impedance at the second high impedance node is lower at any given frequency than the impedances at the first and third high impedance nodes. The first frequency compensating capacitor is coupled between the first and third nodes and the second frequency compensating capacitor is coupled between the third and second nodes.

Abstract: The combination of integrated injection logic (I.sup.2 L) and linear circuitry permits fabrication of a highly dense analog-to-binary coded decimal (A-to-BCD) converter. The heart of the A-to-BCD converter is a linear-I.sup.2 L plurality of high density variable current sinks which are proportional to each other in combination with I.sup.2 L gating techniques. These variable current sinks, when used in combination with the I.sup.2 L constant current sources, current sensing means, and I.sup.2 L logic, provide a highly dense A-to-BCD converter.

Abstract: The bus terminating circuit isolates itself from a bus in response to the magnitude of a power supply voltage decreasing below a predetermined threshold level. The bus terminating circuit includes a bus termination voltage divider network having one terminal coupled through a threshold sensing device to one of the pair of power supply terminals, another terminal coupled to the bus and a further terminal coupled through a transistor to the other of the pair of power supply terminals. Another threshold sensing circuit is coupled between one of the pair of power supply terminals and the control electrode of the transistor. The threshold sensing circuits are responsive to the magnitude of the power supply voltage falling below the predetermined threshold level to render devices of the threshold sensing circuits non-conductive and thereby electrically isolate the bus termination network from the bus.

Abstract: An amplifier circuit is disclosed which includes a current supply circuit having a field effect transistor and negative feedback for degenerating the magnitude of the current supplied thereby. The negative feedback can be provided by a diffused resistor connected between the gate and source electrodes of the current supply field effect transistor. A differential amplifier which includes a pair of differentially coupled amplifying field effect transistors is coupled to the current supply circuit. The negative feedback enables the current supply device to provide a current which compensates the differentially coupled field effect transistors over processing while not deleteriously affecting the temperature characteristics thereof. A bipolar diode and a bipolar transistor can be included in the current supply for enabling the resistor to take up less chip area and for allowing more flexibility in the design of the geometry of the current supply, field effect transistor.

Abstract: An analog subsystem is disclosed which can be included in a single monolithic, integrated circuit chip and which is for use with a digital subsystem to form a dual ramp analog-to-digital converter. A current steering network included in the analog subsystem is connected to a reference current source and to an input voltage-to-current converter. An integrator is connected to the output of the current steering network, and a comparator is connected to the output of the integrator. The current steering network selectively conducts the current from the converter to charge the integrator for a predetermined period of time, which is terminated by the application of a signal to the current steering network by the digital subsystem. The network then conducts the current from the constant reference current source to discharge the integrator which ultimately triggers the comparator.

Abstract: A digital-to-analog converter circuit suitable for implementation as an integrated circuit in integrated-injection-logic form, and a method for regulating the collector current in a plurality of integrated-injection-logic transistors are disclosed. A plurality of switching transistors are connected to digital input terminals and the currents conducted by the plurality of switching transistors are summed to yield an analog output current. An injection bar shared by each of the switching transistors provides drive current to the plurality of switching transistors. The injection bar is also shared by one or more reference transistors, the current in which is determined by a current source. A feedback circuit is used to regulate the bias of the common injection bar such that the current conducted by each switching device corresponds to the current conducted by each reference device.

Abstract: The current supply includes a constant current supply transistor which is cascoded with an output transistor. The current supply also has a feedback circuit including two current mirrors connected between the base and emitter electrodes of the output transistor. The feedback circuit and the output transistor clamps the potential at the collector electrode of the current supply transistor to a constant magnitude to substantially eliminate base width modulation therein. Also, the feedback circuit provides a current into the emitter of the output transistor having an instantaneous magnitude substantially equal to the magnitude of the base current flowing out of the base electrode of the output transistor. Consequently, the collector current of the output transistor remains substantially constant even though the variation of the magnitude of the load voltage at the output terminal of the current supply circuit causes the magnitude of the base current of the output transistor to change.

Abstract: The circuit includes a reference cell having four NPN transistors with the base-to-emitter junctions thereof connected in a loop with a resistor. A separate bias circuit is connected to at least one of the transistors of the cell. The collector-to-emitter paths of a first pair of the transistors are connected in series and the collector-to-emitter paths of a second pair of the transistors of the cell are also connected in series. The configuration of the cell enables the emitter of one of the transistors thereof to drive a plurality of controlled NPN current supply transistors so that a reference current developed in the resistor can be provided to plurality of circuit points requiring a reference current of a regulated magnitude which has a predetermined temperature coefficient.

Abstract: A monolithic amplifier circuit including a differential stage, a differential-to-single ended converter stage, a bias circuit and complementary push-pull output transistors is disclosed. The bias circuit is comprised of a current supply, two semiconductor bias devices and two current sinks. The junctions of the bias devices are connected in series across the junctions of the complementary output transistors to provide bias and to compensate for temperature and process variations in the output transistors. One of the bias devices and one of the current sinks are connected in one parallel path and the other bias device and the other current sink are connected in another parallel path through which most of the current from the current supply flows. This parallel connection enables utilization of minimum geometry bias devices in addition to facilitating precise and predictable control of the bias voltages and currents.

Abstract: A circuit is disclosed which provides first and second control voltages for controlling the gains of first and second variable gain amplifiers such that the relative gains provided by the first and second amplifiers can be varied while maintaining the total power gain provided by the first and second amplifiers substantially constant. The first and second control voltages are generated by passing first and second primary currents across semiconductor junctions. The first and second primary currents are controlled respectively by first and second secondary currents, the secondary currents being substantially proportional to the square of the respective primary current. The circuit allows the ratio of the secondary currents to be varied while maintaining the sum of the secondary currents substantially constant. The primary currents are thereby varied such that the sum of the squares of the primary currents remains substantially constant.

Abstract: The disclosed unity gain amplifier circuit includes current supplies, current sinks, input, output and feedback transistors and an inverting gain stage. The negative feedback transistor stabilizes the quiescent signals and enables the magnitude of the amplifier output signal to follow the magnitude of the amplifier input signal. The gain stage, which is connected between the current supplies, the current sinks, and the input and feedback transistors, utilizes undesired signals occurring therein to cancel each other so that the undesired signals do not adversely effect the magnitude of the amplifier output signal.

Abstract: A quadrature phase detector having a tuned circuit connected between inputs thereof with a voltage variable reactance connected therein and further connected to the output of the phase detector for tuning the tuned circuit in accordance with the output of the phase detector, and a voltage variable capacitor in the tuned circuit connected to receive a signal from a comparator which compares the output of the phase detector to a reference signal so that a signal having a predetermined frequency can be applied to the input of the phase detector and the tuned circuit of the phase detector is tuned to a predetermined reference frequency. The tuned circuit input of the phase detector continually tracks the input signal, which may be a FM color subcarrier signal. Additionally, there is compensation for the inherent nonlinearity in the tuned circuit.

Abstract: A buffer amplifier suitable for being driven by a differential amplifier having a differential-to-single ended converter is disclosed. The buffer amplifier includes a multi-collector input transistor of a first conductivity type and an emitter-follower output transistor of a second conductivity type. The base of the output transistor is connected to a first collector of the input transistor. A bias circuit for the output transistor is connected to the first collector of the input transistor and to the base of the output transistor. A negative feedback network is connected between the emitter of the output transistor and the base and second collector of the input transistor to stabilize the quiescent output voltage. Current sources are utilized for maximizing the amplitude of the dynamic output voltage and for facilitating temperature independence.