Patents Represented by Attorney Mayer Fortkort & Williams, PC
  • Patent number: 6638259
    Abstract: A modified medical device for delivery of a pharmaceutically active material is described. The present inventors have found that many conventional medical devices contain a metallic component that comes into contact with a pharmaceutically active material during use, and that the contact substantially reduce the pharmaceutical effectiveness of the pharmaceutically active material. The invention described herein concerns numerous modifications to the metallic component that are effective to prevent such a substantial reduction in pharmaceutical effectiveness.
    Type: Grant
    Filed: October 28, 1999
    Date of Patent: October 28, 2003
    Assignee: SciMed Life Systems, Inc.
    Inventors: Maria Palasis, Louis Ellis, Timothy Mickley
  • Patent number: 6639809
    Abstract: An apparatus and method for mounting an electronic component device directly to a plug in board within an electronic product thereby eliminating differential movement between the mounting surface of a mounting bracket holding an electrical component device, and the plug in board to which the component device is attached during transportation or use. By eliminating differential/relative movement between the anchoring surface of the mounting bracket and the plug in board commonly found in conventional applications, the stresses generated by differential movement of the connection leads of the mounted component device, relative to the plug in board, and the concomitant potential for degradation of component device performance resulting therefrom, are eliminated.
    Type: Grant
    Filed: October 26, 2000
    Date of Patent: October 28, 2003
    Assignee: General Instrument Corporation
    Inventors: Brett Rosen, Robert Joseph Chilton, III, Warren Panama Johnson
  • Patent number: 6636006
    Abstract: A deflection yoke for use in a cathode ray tube includes a switching circuit, which is coupled to each vertical coil. The deflection yoke employs two pairs of vertical coils. The vertical coil pairs can be two pairs of saddle type coils, one pair of saddle type coils and one pair of toroidal type coils, or a divided pair of saddle type coils to make two pairs of saddle type coils. The deflection in the first quarter region from the top and the last quarter region at the bottom of the CRT screen is provided by one coil when energized by the vertical deflection current switched through it. The deflection in the two middle quarter regions of the CRT screen is provided by a second coil when energized by the vertical deflection current switched through it. One vertical coil pair is optimized to correct convergence error in the top and bottom quarter portions of the CRT screen. The other vertical coil pair is optimized to correct convergence error in the middle portion of the CRT screen.
    Type: Grant
    Filed: December 6, 2001
    Date of Patent: October 21, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Yoshihiko Usami
  • Patent number: 6630402
    Abstract: In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.
    Type: Grant
    Filed: November 21, 2001
    Date of Patent: October 7, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato
  • Patent number: 6631222
    Abstract: An optical switch includes at least one input port for receiving a WDM optical signal having a plurality of wavelength components, at least three output ports, and a plurality of wavelength selective elements each selecting one of the wavelength components from among the plurality of wavelength components. A plurality of optical elements are also provided, each of which are associated with one of the wavelength selective elements. Each of the optical elements direct the selected wavelength component that is selected by its associated selected element to a given one of the output ports independently of every other wavelength component. The given output port is variably selectable from among all the output ports.
    Type: Grant
    Filed: May 16, 2000
    Date of Patent: October 7, 2003
    Assignee: Photuris, Inc.
    Inventors: Jefferson L. Wagener, Thomas Andrew Strasser
  • Patent number: 6627949
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: September 30, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6627951
    Abstract: A method for making trench DMOS is provided that utilizes polycide and refractory techniques to make trench DMOS which exhibit low gate resistance, low gate capacitance, reduced distributed RC gate propagation delay, and improved switching speeds for high frequency applications.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: September 30, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6624560
    Abstract: A depression in the windings of a horizontal coil at a predetermined location in a deflection yoke of a cathode ray tube corrects for multiple types of mis-convergence. In particular, the depression in the windings is disposed in a “neck” portion of the deflection yoke, which incorporates a horizontal deflection coil disposed on a saddle type mold die. A deflection yoke for deflecting electron beams of a color CRT includes a horizontal deflection coil disposed on a saddle type mold die that has a funnel section and a neck section connected along a horizontal axis parallel to the centerline of the deflection yoke. A portion of the neck section of the deflection yoke includes an offset relative to the profile (relative to the horizontal axis) of the windings of the horizontal coil that creates a depressed area in the windings of the horizontal deflection coil.
    Type: Grant
    Filed: May 22, 2001
    Date of Patent: September 23, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: Yoshihiko Usami
  • Patent number: 6623619
    Abstract: Electrochemical sensor for determining analyte in the presence of interferent, particularly carbon monoxide in the presence of hydrogen. An electrochemical cell is designed so that current flow resulting from reference electrode potential shift caused by interferent cancels out the current flow caused by interferent at the working electrode. Another electrochemical cell corrects for interferent concentration using the potential difference between a reference electrode in contact with interferent and a referent electrode not affected by inteferent.
    Type: Grant
    Filed: May 14, 2001
    Date of Patent: September 23, 2003
    Assignee: Alphasense Limited
    Inventors: John R Saffell, Michael L Hitchman, Darryl H Dawson
  • Patent number: 6624568
    Abstract: An organic optoelectronic device structure is provided that comprises the following: (a) a polymer substrate layer; (b) a first barrier region, which comprises two or more planarizing layers and two or more high-density layers, disposed over the polymer substrate layer; (c) a second barrier region, which comprises two or more planarizing layers, two or more high-density layers and at least one layer of an absorbing material that absorbs water, oxygen or both water and oxygen, disposed over the first barrier region; and (d) an organic optoelectronic device, which is selected from an organic light emitting diode, an organic electrochromic display, an organic photovoltaic device and an organic thin film transistor, disposed between the first and second barrier regions. The first and second barrier regions in this structure restrict transmission of water and oxygen from an outer environment to the optoelectronic device.
    Type: Grant
    Filed: March 28, 2001
    Date of Patent: September 23, 2003
    Assignee: Universal Display Corporation
    Inventor: Jeffrey Alan Silvernail
  • Patent number: 6624494
    Abstract: A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 23, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 6619309
    Abstract: An excess flow valve includes a linear actuator that effectively isolates a defective CRT from others under preparation when the defective CRT causes the vacuum drawn on the exhaust cart to be compromised. During the manufacture of CRT's a manufacturing step requires that a vacuum be drawn on all CRT's while baking in an exhaust oven. This process is usually performed simultaneously on a plurality of CRT's connected to an exhaust cart by a manifold such that if a defect were to occur to one CRT that breaks breaking the vacuum, all the other CRT's under preparation would be compromised. This excess flow valve with the linear acutator and a method of operating it prevents excess damage to otherwise non-damaged CRTs.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: September 16, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Christopher Monks
  • Patent number: 6621107
    Abstract: A merged device is that comprises a plurality of MOSFET cells and a plurality of Schottky rectifier cells, as well as a method of designing and making the same. According to an embodiment of the invention, the MOSFET cells comprise: (a) a source region of first conductivity type formed within an upper portion of a semiconductor region, (b) a body region of second conductivity type formed within a middle portion of the semiconductor region, (c) a drain region of first conductivity type formed within a lower portion of the semiconductor region, and (d) a gate region provided adjacent the source region, the body region, and the drain region. The Schottky diode cells in this embodiment are disposed within a trench network and comprise a conductor portion in Schottky rectifying contact with the lower portion of the semiconductor region. At least one MOSFET cell gate region is positioned along a sidewall of the trench network and adjacent at least one Schottky diode cell in this embodiment.
    Type: Grant
    Filed: August 23, 2001
    Date of Patent: September 16, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6620691
    Abstract: A method for making trench DMOS is provided that improves the breakdown voltage of the oxide layer in a device having at least a first trench disposed in the active region of the device and a second trench disposed in the termination region of the device. In accordance with the method, mask techniques are used to thicken the oxide layer in the vicinity of the top corner of the second trench, thereby compensating for the thinning of this region (and the accompanying reduction in breakdown voltage) that occurs due to the two-dimensional oxidation during the manufacturing process.
    Type: Grant
    Filed: November 20, 2001
    Date of Patent: September 16, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Patent number: 6618500
    Abstract: A method for color conversion applying minimal surface theory to the formation of the volumes in a three-dimensional color cube. Volume center points on the color cube are selected as entries in a color look-up table, and these center points are plotted on the color cube. Spheres centered about each volume center point are created, and the discrete locations in the color cube falling within each sphere are associated with the CLUT entry corresponding to that volume center point. The radii of the spheres are incrementally increased, and the discrete locations falling within the enlarged spheres are associated with the corresponding CLUT entry. As the spheres enlarge they begin to intersect. The intersection of the spheres form planes which divide the discrete locations such that each discrete location is associated with the closest volume center point.
    Type: Grant
    Filed: December 7, 1999
    Date of Patent: September 9, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Thomas P. Dawson
  • Patent number: 6614057
    Abstract: An organic optoelectronic device structure is provided.
    Type: Grant
    Filed: February 7, 2001
    Date of Patent: September 2, 2003
    Assignee: Universal Display Corporation
    Inventors: Jeffrey Alan Silvernail, Kenneth L. Urbanik
  • Patent number: 6614953
    Abstract: An all-optical, optical cross-connect includes first and second pluralities of multiport optical devices. Each of the first plurality of multiport optical devices have at least one input port for receiving a WDM optical signal and a plurality of output ports for selectively receiving one of more wavelength components of the optical signal. Each of the second plurality of multiport optical devices have a plurality of input ports for selectively receiving one of more wavelength components of the optical signal and at least one output port for selectively receiving one of more wavelength components of the optical signal. At least one of the first or second plurality of multiport optical devices are all-optical switches that can route every wavelength component independently of every other wavelength component.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: September 2, 2003
    Assignee: Photuris, Inc.
    Inventors: Thomas Andrew Strasser, Per Bang Hansen, Jefferson L. Wagener
  • Patent number: 6611374
    Abstract: A method and apparatus is provided for controlling the optical output power from an optical amplifier arrangement. The arrangement includes a rare-earth doped fiber for imparting gain to an optical input signal propagating therethrough, a pump source for supplying pump power to the rare-earth doped fiber, and a tap for receiving a portion of the output power generated by the rare-earth doped fiber and converting it to a control signal. A controller is also provided for receiving the control signal and generating a bias current in response thereto for driving the pump source. The method begins by receiving an optical input signal that is being amplitude modulated at a prescribed frequency. The slew rate of the controller is adjusted so that the bias current drives the pump source to generate pump power that cannot vary at a rate greater than a slew-rate limit established by the controller. In this way resonance between the input signal and the frequency of the feedback control loop can be avoided.
    Type: Grant
    Filed: January 31, 2002
    Date of Patent: August 26, 2003
    Assignee: General Instrument Corporation
    Inventors: Eric James Converse, David Ciaffa, Charles John Donaldson
  • Patent number: 6606360
    Abstract: A method and apparatus for asynchronously receiving a stream of data. The method and apparatus operate to detect edges within the stream of data and track a transmitted clock using multiple locally-generated clock phases. Moreover, the method and apparatus determine whether each edge arrives early or late relative to an expected arrival time and use the determination whether an edge arrived early or late in a receiver decision process. An exemplary embodiment of the apparatus to recover a clock from a stream of data includes an edge buffer, an edge processor, a multi-phase clock and an elastic buffer. The edge buffer receives the data stream and outputs an edge signal that indicates detection of an edge within the data stream. The edge processor is coupled to the edge buffer, determines an average phase of the detected edges and outputs a data signal and the average phase.
    Type: Grant
    Filed: December 30, 1999
    Date of Patent: August 12, 2003
    Assignee: Intel Corporation
    Inventors: David S. Dunning, Chamath Abhayagunawardhana
  • Patent number: 6602769
    Abstract: A bi-directional transient voltage suppression device with symmetric current-voltage characteristics has a lower semiconductor layer of first conductivity type, an upper semiconductor layer of first conductivity type, and a middle semiconductor layer adjacent to and disposed between the lower and upper layers having a second opposite conductivity type, such that upper and lower p−n junctions are formed. The middle layer has a net doping concentration that is highest at a midpoint between the junctions. Furthermore, the doping profile along a line normal to the lower, middle and upper layers is such that, within the middle layer the doping profile on one side of a centerplane of the middle layer mirrors the doping profile on an opposite side. In addition, an integral of the net doping concentration of the middle layer taken over the distance between the junctions is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: August 5, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Willem G. Einthoven, Lawrence LaTerza, Gary Horsman, Jack Eng, Danny Garbis