Patents Represented by Attorney Mayer Fortkort & Williams, PC
  • Patent number: 6603986
    Abstract: A method and system for controlling an accessory function by a cellular telephone are disclosed. In accordance with the method, the cellular telephone generates a message payload comprising a command to set a selected register on an accessory device to a selected value. The cellular telephone transmits the message payload to the accessory device. The selected value is stored in the selected register on the accessory device in response to the message payload. The accessory device periodically reads the contents of the selected register. The accessory device controls the accessory function in response to the contents read from the selected register. The simple message protocol uses memory and bandwidth resources efficiently, and allows additional accessory functions to be readily controlled without significant modifications to the protocol.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: August 5, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Theodore S. Bozoukov
  • Patent number: 6600204
    Abstract: A bi-directional transient voltage suppression device is provided. The device comprises: (a) a lower semiconductor layer of p-type conductivity; (b) an upper semiconductor layer of p-type conductivity; (c) a middle semiconductor layer of n-type conductivity adjacent to and disposed between the lower and upper layers such that lower and upper p-n junctions are formed; (d) a mesa trench extending through the upper layer, through the middle layer and through at least a portion of the lower layer, such that the mesa trench defines an active area for the device; and (e) an oxide layer covering at least portions of the walls of the mesa trench that correspond to the upper and lower junctions, such that the distance between the upper and lower junctions is increased at the walls. The integral of the net middle layer doping concentration of this device, when taken over the distance between the junctions, is such that breakdown, when it occurs, is punch through breakdown, rather than avalanche breakdown.
    Type: Grant
    Filed: July 11, 2001
    Date of Patent: July 29, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Willem G. Einthoven, Anthony Ginty, Aidan Walsh
  • Patent number: 6597111
    Abstract: Disclosed are protected OLED devices comprising (a) a substrate; (b) an active region positioned on the substrate, wherein the active region comprises an anode layer, a cathode layer and a light-emitting layer disposed between the anode layer and the cathode layer; (c) a composite barrier layer disposed over the active region and/or over a surface of the substrate, the composite barrier layer comprising an alternating series of one or more polymeric planarizing sublayers and one or more high-density sublayers; and, (d) a thin carbon layer disposed between at least one polymeric planarizing sublayer and a region of the OLED device that is selected from the group consisting of the substrate, an adjacent high-density sublayer, and the active region. The composite barrier layer is provided to protect the active region of the OLED device from environmental elements such as oxygen and moisture. The thin carbon layer is provided to improve adhesion between adjacent layers.
    Type: Grant
    Filed: November 27, 2001
    Date of Patent: July 22, 2003
    Assignee: Universal Display Corporation
    Inventors: Jeffrey Alan Silvernail, Michael Stuart Weaver
  • Patent number: 6593619
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
    Type: Grant
    Filed: June 2, 2000
    Date of Patent: July 15, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6593620
    Abstract: An integrated circuit having a plurality of trench Schottky barrier rectifiers within one or more rectifier regions and a plurality of trench DMOS transistors within one or more transistor regions.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: July 15, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Yan Man Tsui, Koon Chong So
  • Patent number: 6584357
    Abstract: A non-invasive system and process for converting sensory data, e.g., visual, audio, taste, smell or touch, to neural firing time differences in a human brain and using acoustic signals to generate the neural firing time differences. Data related to neural firing time differences, the acoustic signals, and a user's response map may be stored in memory. The user's response map may be used to more accurately map the calculated neural firing time differences to the correct neural locations.
    Type: Grant
    Filed: October 17, 2000
    Date of Patent: June 24, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: Thomas P. Dawson
  • Patent number: 6580141
    Abstract: A Schottky rectifier is provided. The Schottky rectifier comprises: (a) a semiconductor region having first and second opposing faces, with the semiconductor region comprising a cathode region of first conductivity type adjacent the first face and a drift region of the first conductivity type adjacent the second face, and with the drift region having a lower net doping concentration than that of the cathode region; (b) one or more trenches extending from the second face into the semiconductor region and defining one or more mesas within the semiconductor region; (c) an insulating region adjacent the semiconductor region in lower portions of the trench; (d) and an anode electrode that is (i) adjacent to and forms a Schottky rectifying contact with the semiconductor at the second face, (ii) adjacent to and forms a Schottky rectifying contact with the semiconductor region within upper portions of the trench and (iii) adjacent to the insulating region within the lower portions of the trench.
    Type: Grant
    Filed: June 1, 2001
    Date of Patent: June 17, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So
  • Patent number: 6576952
    Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.
    Type: Grant
    Filed: January 17, 2002
    Date of Patent: June 10, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Patent number: 6576985
    Abstract: The present invention provides a semiconductor device packaging assembly and method for manufacturing the assembly. Preferably, the method of the present invention is used to assemble a plurality of semiconductor chips, such that the throughput of assembly can be enhanced, by providing a bottom frame matrix including a plurality of bottom frame units, each of which unit includes a bottom supporting portion and a bottom frame portion; providing a bridge frame including a plurality of bridge frame units, each of which unit includes a bridge frame portion and a plurality of conducting bars; placing each of the semiconductor chips on each of the bottom supporting portions, respectively; and bonding each bottom frame unit and each bridge frame unit together, wherein, the conducting bars extending from each bridge frame portion toward corresponding chips are electrically coupled to bonding areas of the corresponding chips.
    Type: Grant
    Filed: January 18, 2001
    Date of Patent: June 10, 2003
    Assignee: General Semiconductor Taiwan, Ltd.
    Inventors: Max Chen, Ching Lu Hsu, Kuang Hann Lin, Yan-Man Tsui
  • Patent number: 6576516
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: June 10, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6576351
    Abstract: An organic optoelectronic device structure and a method of making the same. The structure comprises: (a) a first barrier region comprising (i) a first composite layer stack and (ii) a second composite layer stack attached to the first composite layer stack, (b) an organic optoelectronic device selected from an organic light emitting diode, an organic electrochromic display, an organic photovoltaic device and an organic thin film transistor; and (c) at least one additional barrier region, wherein the at least one additional barrier region cooperates with the first barrier region to restrict transmission of water and oxygen to the optoelectronic device from an outer environment.
    Type: Grant
    Filed: February 16, 2001
    Date of Patent: June 10, 2003
    Assignee: Universal Display Corporation
    Inventor: Jeffrey Alan Silvernail
  • Patent number: 6574273
    Abstract: A method and apparatus for decoding an input MPEG video stream are provided that includes a core processor with a very large instruction word (VLIW) processor and a co-processor that includes a variable length decoder (VLD) for decoding the MPEG video stream. The input MPEG video stream is organized into macroblocks, wherein each macroblock includes a header for a macroblock that is not decoded, and encoded data for a macroblock whose header is previously decoded by VLD. Thereafter, VLD decodes the encoded video data of a first macroblock whose header has been decoded, and decodes the header of a second (current) macroblock. VLIW then performs motion compensation on a current macroblock based upon reference data of a previously decoded macroblock. VLIW also adds a fake slice start code and fake macroblock data at the end of each picture into the input MPEG video data stream; and utilizes the fake slice start code and fake macroblock data to skip to a next picture.
    Type: Grant
    Filed: January 12, 2000
    Date of Patent: June 3, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Amelia Carino Luna, Jason N. Wang, Richard L. Williams
  • Patent number: 6573648
    Abstract: A deflection yoke for deflecting electron beams of a color cathode ray tube includes a saddle type horizontal deflection coil, which has a front bend section and a neck bend section. The neck bend section includes a pair of openings in the winding distribution. Each of the openings is disposed at a disposition angle relative to a horizontal axis through the neck bend section of approximately ten degrees and at a predetermined distance from a center of the neck bend section within a range from approximately three millimeters to approximately fifteen millimeters. Each of the openings has a substantially triangular shape, trapezoidal or semicircular shape. A resulting XH and HCR mis-convergence curve of the deflection yoke of the present invention passes through the origin, thereby making it possible to simultaneously correct both XH and HCR mis-convergence to zero.
    Type: Grant
    Filed: November 19, 1999
    Date of Patent: June 3, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: Yoshihiko Usami
  • Patent number: 6566201
    Abstract: A method for fabricating a high voltage power MOSFFT having a voltage sustaining region that includes doped columns formed by rapid diffusion. A high voltage semiconductor device having a substrate of a first or second conductivity type, an epitaxial layer of the first conductivity on the substrate, and a voltage sustaining region formed in the epitaxial layer, the voltage sustaining region including a column having a second conductivity type formed along at least outer sidewalls of a filled trench, the column including at least one first diffused region and a second diffused region, the first diffused region being connected by the second region and the second region having a junction depth measured from the trench sidewall that is less than the junction depth of the first region and a third region of a second conductivity type that extends from the surface of the epitaxial layer to intersect at least one of the first and second regions of second conductivity type.
    Type: Grant
    Filed: December 31, 2001
    Date of Patent: May 20, 2003
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 6565222
    Abstract: A video projection device includes a cabinet having front and rear sections and a projection tube for projecting a video image. The video projection device also includes a screen located in the front section of the cabinet. The screen has a first surface onto which the video image is projected and a second surface for displaying the video image so that it is observable by a viewer. A mirror is arranged in the cabinet for reflecting light to the first surface of the screen. The mirror is a composite laminate mirror that includes a rigid substrate and a reflective sheet laminated to the rigid substrate. The rigid substrate may be a glass substrate and the reflective sheet may be a flexible plastic sheet. The reflective sheet may have a multilayer construction that includes a metallic film. The reflective sheet may alternatively include a second substrate and at least one thin film layer deposited on the substrate.
    Type: Grant
    Filed: November 17, 2000
    Date of Patent: May 20, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Fusao Ishii, Joseph A. Marcanio
  • Patent number: 6558984
    Abstract: A trench Schottky barrier and a method of making the same in which the rectifier has a semiconductor region having first and second opposing faces; the semiconductor region having a drift region of a first conductivity type adjacent the first face and a cathode region of the first conductivity type adjacent the second face; the drift region having a lower net doping concentration than that of the cathode region. The rectifier also has a plurality of trenches extending into the semiconductor region from the first face; the trenches defining a plurality of mesas within the semiconductor region, and the trenches forming a plurality of trench intersections.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: May 6, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato
  • Patent number: 6560751
    Abstract: A method for determining compliance with design specifications is provided. In accordance with the method, a product is provided which is characterized by k parameters, k≧2, wherein, for n=1 to k, the nth parameter has a design specification PnDesign and an actual value of PnActual, and wherein dn=PnDesign−PnActual. The value of Δ Actual = [ ∑ n = 1 k ⁢   ⁢ d n 2 ] 1 / 2 is then determined. If &Dgr;Actual≦&Dgr;Design, where &Dgr;Design is the total design tolerance for the product, then the product is deemed to comply with design specifications.
    Type: Grant
    Filed: November 6, 2001
    Date of Patent: May 6, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventor: John Douglas Rose
  • Patent number: 6554438
    Abstract: A video projection device includes a cabinet having front and rear sections and a projection tube for projecting a video image. The video projection device also includes a screen located in the front section of the cabinet. The screen has a first surface onto which the video image is projected and a second surface for displaying the video image so that it is observable by a viewer. A mirror is arranged in the cabinet for reflecting light to the first surface of the screen. The mirror is a composite laminate mirror that includes a rigid substrate and a reflective sheet laminated to the rigid substrate. The rigid substrate may be a glass substrate and the reflective sheet may be a flexible plastic sheet. The reflective sheet may have a multilayer construction that includes a metallic film. The reflective sheet may alternatively include a second substrate and at least one thin film layer deposited on the substrate.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: April 29, 2003
    Assignees: Sony Corporation, Sony Electronics, Inc.
    Inventors: Fusao Ishii, Joseph A. Marcanio
  • Patent number: 6555895
    Abstract: In a first aspect of the invention, a modified semiconductor substrate is provided. The modified substrate comprises: (1) a semiconductor substrate; (2) at least one buffer layer provided over at least a portion of the substrate; and (3) a plurality of trenches comprising (a) a plurality of internal trenches that extend into the semiconductor substrate and (b) at least one shallow peripheral trench that extends into the at least one buffer layer but does not extend into the semiconductor substrate. In another aspect, a method of selectively providing trenches in a semiconductor substrate is provided. According to a further aspect of the invention, a trench DMOS transistor structure that includes at least one peripheral trench and a plurality of internal trenches is provided.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: April 29, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, Yan Man Tsui
  • Patent number: 6553517
    Abstract: A method and apparatus is provided for interleaving and de-interleaving frame symbols using a single memory buffer. Input frame symbols are read out in an interleaved sequence (or de-interleaved sequence) on a symbol by symbol basis. Frame symbols following the input frame symbols are written into memory locations from where the input frame symbols were read.
    Type: Grant
    Filed: April 7, 2000
    Date of Patent: April 22, 2003
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventor: Mohit K. Prasad