Patents Represented by Attorney, Agent or Law Firm McDermott, Will & Emery
-
Patent number: 8344320Abstract: A lens adjustment method and a lens adjustment system which adjust a plurality of multi-pole lenses of an electron spectrometer attached to a transmission electron microscope, optimum conditions of the multi-pole lenses are determined through simulation based on a parameter design method using exciting currents of the multi-pole lenses as parameters.Type: GrantFiled: January 6, 2011Date of Patent: January 1, 2013Assignee: Hitachi High-Technologies CorporationInventors: Shohei Terada, Yoshihumi Taniguchi, Kazutoshi Kaji
-
Patent number: 8344522Abstract: The invention provides a solder structure which is least likely to develop Sn whiskers and a method for forming such a solder structure. The solder structure includes an Sn alloy capable of a solid-liquid coexistent state and an Au (or Au alloy) coating covering at least part of the surface of the Sn alloy. The Au covering is a film that covers and coats at least part of the surface of the Sn alloy. As a preferable mode, the Au coating forms a netlike structure on the surface of the Sn alloy. The thickness of the Au coating is, for instance, 1 to 5 ?m.Type: GrantFiled: March 18, 2009Date of Patent: January 1, 2013Assignee: Sanyo Electric Co., Ltd.Inventors: Hideki Mizuhara, Hajime Kobayashi, Toshiya Shimizu
-
Patent number: 8345470Abstract: A control circuit supplies a word line drive voltage to one of m word lines which corresponds to a memory cell to which data is to be written, during a word line drive period including a first period and a second period following the first period, to decrease current capabilities of first and second load transistors included in the memory cell during the first period, and increase the current capabilities of the first and second load transistors during the second period.Type: GrantFiled: January 11, 2011Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Katsuji Satomi, Toshio Terano, Kazuhiro Takemura, Marefusa Kurumada
-
Patent number: 8341933Abstract: A method of cooling a rocket engine that includes removal of a gaseous propellant from a tank containing liquid propellant, thereby cooling the propellant in the tank, cooling a rocket engine with a coolant, thereby heating the coolant, and transferring heat from the heated coolant into the propellant in the tank, thereby heating the propellant in the tank and maintaining the pressure in the tank. In certain embodiments, the coolant is injected into the rocket engine after transferring heat from the rocket engine to the propellant in the tank.Type: GrantFiled: July 29, 2010Date of Patent: January 1, 2013Assignee: XCOR AerospaceInventors: Jeffrey K. Greason, Daniel L. DeLong, Douglas B. Jones
-
Patent number: 8343085Abstract: The present invention relates to a blood purification apparatus for extracorporeally circulating the blood of a patient so as to purify the blood for medical treatment incorporating a dialyzer and a method for priming the blood purification apparatus, wherein the present invention provides a blood purification apparatus and its priming method which can simply and easily automate the priming operation and also can surely and smoothly perform the bubble purging of the dialyzer.Type: GrantFiled: December 15, 2009Date of Patent: January 1, 2013Assignee: Nikkiso Co., Ltd.Inventors: Masahiro Toyoda, Satoshi Takeuchi
-
Patent number: 8344511Abstract: To provide a semiconductor device which can reduce an electrical resistance between a plug and a silicide region, and a manufacturing method thereof. At least one semiconductor element having a silicide region, is formed over a semiconductor substrate. An interlayer insulating film is formed over the silicide region. A through hole having an inner surface including a bottom surface comprised of the silicide regions is formed in the interlayer insulating film. A Ti (titanium) film covering the inner surface of the hole is formed by a chemical vapor deposition method. At least a surface of the Ti film is nitrided so as to forma barrier metal film covering the inner surface. A plug is formed to fill the through hole via the barrier metal film.Type: GrantFiled: March 7, 2012Date of Patent: January 1, 2013Assignee: Renesas Electronics CorporationInventors: Kazuhito Ichinose, Yukari Imai
-
Patent number: 8344700Abstract: A charging method for charging a secondary battery includes the steps of: (a) performing constant-current charging with a first current; and (b) when a voltage of a secondary battery reaches a first voltage, performing constant-voltage charging at the first voltage. When a temperature of the secondary battery is equal to or higher than a reference temperature in step (a), step (b) includes the steps of (b1) when the voltage of the secondary battery reaches a second voltage lower than the first voltage, performing constant-voltage charging at the second voltage, (b2) after step (b1) and when the temperature of the secondary battery falls below the reference temperature, performing charging with a second current, and (b3) when the voltage of the secondary battery reaches the first voltage, performing constant-voltage charging at the first voltage.Type: GrantFiled: March 3, 2009Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Takeaki Nagashima, Yoshiyuki Nakatamari
-
Patent number: 8343658Abstract: A positive electrode 2 and a negative electrode 3 are contained in a battery case 1 with a separator 4 interposed therebetween. The positive electrode 2 contains manganese dioxide and an alkaline electrolyte, and the negative electrode 3 is a gelled negative electrode containing zinc powder, a gelling agent, and an alkaline electrolyte. The zinc powder contains 15% by mass or higher of fine powder with a particle size smaller than 200 mesh, and 10 to 35% by mass of coarse powder with a particle size of 20 to 80 mesh, and has a specific surface area in the range of 0.025 to 0.080 m2/g.Type: GrantFiled: March 15, 2010Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Shinichi Sumiyawa, Yasuhiko Syoji
-
Patent number: 8344776Abstract: Provided is a memory interface circuit connected to a memory device that outputs a first data signal, and including: a first delay unit delaying a first strobe signal outputted from the memory device by a first delay amount to generate a first delayed strobe signal; a first data latch unit latching the first data signal as a first latched data signal in synchronization with the first delayed strobe signal; a first range calculating unit calculating a first delay range width that is a width of a range of values of the first delay amount which allow the first data latch unit to correctly latch the first data signal as the first latched data signal; and a drive capability setting unit adjusting the drive capability of the memory device so as to widen the first delay range width.Type: GrantFiled: May 17, 2012Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventor: Takahide Baba
-
Patent number: 8344461Abstract: A MOS solid-state imaging device having: a semiconductor substrate provided with a pair of source and drain regions in a pixel area, the pair of source and drain regions constituting part of a transistor in the pixel area; an insulating film formed over the semiconductor substrate; a wiring layer formed over the insulating film; and a contact plug penetrating through the insulating film to connect either one of the pair of source and drain regions with the wiring layer, wherein a surface area of said one of the pair of source and drain regions is silicided, the surface area contacting with the contact plug, and a width of the surface area is equal to a width of the contact plug.Type: GrantFiled: September 29, 2010Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventor: Tomotsugu Takeda
-
Patent number: 8343827Abstract: In a CMIS device, to improve the operating characteristics of an n-channel electric field transistor that is formed by using a strained silicon technique, without degrading the operating characteristics of a p-channel field effect transistor. After forming a source/drain (an n-type extension region and an n-type diffusion region) of an nMIS and a source/drain (a p-type extension region and a p-type diffusion region) of a pMIS, the each source/drain having a desired concentration profile and resistance, a Si:C layer having a desired amount of strain is formed in the n-type diffusion region, and thus the optimum parasitic resistance and the optimum amount of strain in the Si:C layer are obtained in the source/drain of the nMIS. Moreover, by performing a heat treatment in forming the Si:C layer in a short time equal to or shorter than 1 millisecond, a change in the concentration profile of the respective p-type impurities of the already-formed p-type extension region and p-type diffusion region is suppressed.Type: GrantFiled: July 14, 2011Date of Patent: January 1, 2013Assignee: Renesas Electronics CorporationInventors: Tadashi Yamaguchi, Keiichiro Kashihara, Yoji Kawasaki
-
Patent number: 8344515Abstract: A semiconductor device includes a plurality of through vias extending through a substrate. The plurality of through vias are arranged dividedly in three or more via groups. Each of the via groups includes three or more of the through vias that are arranged in two dimensions.Type: GrantFiled: May 18, 2010Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Taichi Nishio, Hiroshige Hirano, Yukitoshi Ota
-
Patent number: 8344524Abstract: This invention provides a wire bonding method, comprising providing an integrated circuit (IC) die having thereon a passivation layer and a plurality of first bonding pads exposed by respective openings in the passivation layer; forming a polymer layer on the passivation layer; forming an adhesive/barrier layer on the polymer layer; forming a metal pad layer on the adhesive/barrier layer; bonding a wire onto the metal pad layer to form a ball bond thereon; and after forming the ball bond on the metal pad layer, running the wire so as to contact the wire with a second bonding pad and forming a wedge bond thereto.Type: GrantFiled: June 20, 2006Date of Patent: January 1, 2013Assignee: Megica CorporationInventors: Chiu-Ming Chou, Shih-Hsiung Lin, Mou-Shiung Lin, Hsin-Jung Lo
-
Patent number: 8343657Abstract: In a lithium secondary battery using a negative electrode having a negative electrode mixture layer formed on a surface of a negative electrode current collector, the mixture layer made of a binder and negative electrode active material particles of silicon and/or a silicon alloy, charge-discharge cycle performance is improved without degrading the capacity per unit volume, by making the negative electrode mixture layer sufficiently adhere to the negative electrode current collector. The negative electrode has a negative electrode mixture layer composed of a binder and negative electrode active material particles of silicon and/or a silicon alloy. The negative electrode mixture layer is formed on a surface of the negative electrode current collector by sintering. Negative electrode active material particles are partially embedded in the negative electrode current collector.Type: GrantFiled: January 24, 2007Date of Patent: January 1, 2013Assignee: Sanyo Electric Co., Ltd.Inventors: Hiroshi Minami, Atsushi Fukui, Yasuyuki Kusumoto
-
Patent number: 8347026Abstract: A memory device according to this invention includes: N internal memory read buses and N internal memory write buses each including a plurality of internal slots; N memory modules; an output data bus and an input data bus each including a plurality of external slots; a read data processing unit which (i) selects, from pieces of data read from the N memory modules via the N internal memory read buses, pieces of data read via two or more internal slots, and (ii) provides the selected pieces of data to external slots of the output data bus; and a write data processing unit which provides each of pieces of data provided via the external slots included in the input data bus, to one of the internal slots included in the N internal memory write buses, so as to write the pieces of data to the N memory modules.Type: GrantFiled: December 18, 2008Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventors: Takashi Yamada, Daisuke Imoto
-
Patent number: 8344482Abstract: In the bevel etching apparatus relating to the present invention, a substrate is inserted between electrically connected electrodes. A high-frequency power source is connected to the electrodes, and ground potential is applied to a support unit that supports the substrate. Gas (atmosphere) is supplied to the gap between the electrodes and the application of the high-frequency electric power to the electrodes causes the generation of atmospheric-pressure glow discharge between the electrode and the substrate. Bevel etching is performed by rotating the substrate along the circumferential direction in this condition. According to this construction, the bevel etching can be simultaneously performed to the front surface, the rear surface and the side of the substrate without causing any configuration change in the substrate.Type: GrantFiled: November 4, 2010Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventor: Shin-ichi Imai
-
Patent number: 8345141Abstract: An imaging device that is able to display an image with an aperture value at the time when actually photographing on a liquid crystal display monitor for displaying an image, in a single-lens reflex digital camera is provided. In a depth-of-field preview mode, a quick return mirror (4) is retracted from an optical path and light is incident on an imaging sensor (11). Then, an imaging optical system is controlled to be in an actual aperture state, and by displaying an image data obtained at the imaging sensor (11) on the liquid crystal display monitor (16) for displaying an image, a plurality of images with aperture values at the time of actually photographing, in other words, actual aperture live view images, can be concurrently displayed simultaneously on the liquid crystal display monitor (16) for displaying an image. By doing so, it is possible to easily compare images with different depths of field, and it is possible to simultaneously photograph images with different depths of field.Type: GrantFiled: December 5, 2006Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventor: Naoto Yumiki
-
Patent number: 8342589Abstract: Trailers are described that include a chassis, a set of wheels for rollably supporting the chassis on the ground, and a rigid container carried by the chassis. The rigid container comprises a floor, a sidewall, an access door for loading/unloading materials into the container, and a convertible rigid roof. The convertible roof is movable between a closed position which permits waste or other materials to be compressed into the trailer, and an open position which permits the trailer to be loaded with bulk goods from the top. The convertible roof includes movable rigid panels, and a locking bar for holding the panels closed and connecting the opposite sidewalls of the trailer to each other against the expansion pressure exerted by loosely compressed materials transported in the trailer. The panels may be rotating panels hinged to a wall, or may be provided as sliding panels running in tracks.Type: GrantFiled: November 18, 2011Date of Patent: January 1, 2013Assignee: Tital Trailers, Inc.Inventor: Michael Kloepfer
-
Patent number: 8344692Abstract: A charging device includes an air nozzle that prevents power-feeding-side terminals from becoming wet by blasting air, fitting switches operated when a power feeding connector is removed from a connector holding portion, and an ECU that activates an air compressor and a vacuum pump on the basis of operations of the fitting switches. The power-feeding-side terminals can be prevented from becoming wet while the power feeding connector is attached to a power receiving connector of an electric vehicle after being removed from the connector holding portion.Type: GrantFiled: June 8, 2010Date of Patent: January 1, 2013Assignee: Fuji Jukogyo Kabushiki KaishaInventor: Masato Sakurai
-
Patent number: 8344786Abstract: A semiconductor integrated circuit includes a level shift circuit which is located so that a second IO cell region is interposed between the level shift circuit and a first IO cell region, and converts a signal output from an IO cell of the first IO cell region into a signal having an amplitude of a second voltage and outputs the resultant signal, and an internal circuit which is operated using the signal having the amplitude of the second voltage output from the level shift circuit. A signal interconnect via which the signal output from the IO cell of the first IO cell region is input to the level shift circuit is provided between the IO cell of the first IO cell region and the level shift circuit, extending over or in an IO cell of the second IO cell region.Type: GrantFiled: July 7, 2011Date of Patent: January 1, 2013Assignee: Panasonic CorporationInventor: Masahiro Gion