Patents Represented by Attorney McGinn IP Law Group, PLLC
  • Patent number: 8298900
    Abstract: A method of manufacturing a nonvolatile semiconductor storage device includes sequentially forming a charge storage film, a conductive film, and a mask film on a semiconductor substrate, sequentially removing the mask film, the conductive film, and the charge storage film at a given portion to form a groove, forming a word gate electrode to fill in the groove whose inside is covered with an insulating film, after said forming the word gate electrode, removing the mask film, after said removing the mask film, forming a spacer film to cover the conductive film and the word gate electrode, etching back the spacer film to form a spacer layer on both sides of the word gate electrode through the insulating film, removing the conductive film and the charge storage film to form a control gate electrode, and forming a source drain diffusion layer.
    Type: Grant
    Filed: October 11, 2011
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Fumihiko Hayashi
  • Patent number: 8297307
    Abstract: To provide a relief valve structure for an oil pump, which is capable of appropriately controlling/switching the discharge pressure and flow rate of oil to an optimum condition in low, middle and high speed regions of an engine. The relief valve structure has: a relief valve having formed therein a valve flow path for communicating between a valve head part and an outer circumferential side part; a valve housing in which a valve passage accommodating the relief valve is formed; a relief flow-in part formed on an axial direction one end side of the valve passage and communicating with the valve passage; a first discharge part formed in the valve housing and communicating with the valve flow path by the movement of the relief valve; and a second discharge part that is opened by allowing the valve head part to pass therethrough. The second discharge part is positioned nearer to the relief flow-in part than the first discharge part.
    Type: Grant
    Filed: September 29, 2009
    Date of Patent: October 30, 2012
    Assignee: Yamada Manufacturing Co., Ltd.
    Inventors: Yoshitaka Kurokawa, Masahiro Kasahara, Yoshiro Umezawa
  • Patent number: 8299807
    Abstract: A foreign objection detection sensor has a lengthy sensor part having a sensor electrode having a first sensor electrode which detects a proximity of a foreign object and a second sensor electrode which detects a contact of the foreign object, a sensor terminal part provided at one end of the sensor part, a leading wire pulled out from the sensor terminal part, the leading wire being electrically connected to the sensor electrode at the sensor terminal part to provide a proximity detecting function for detecting the proximity of the foreign object to the sensor part and a contact detecting function for detecting the contact of the foreign object to the sensor part. The sensor terminal part has a support member which supports a detection circuit unit electrically connected to the sensor electrode to carry out the proximity detecting function and the contact detecting function together with the sensor electrode. The detection circuit unit is disposed in the support member.
    Type: Grant
    Filed: February 24, 2010
    Date of Patent: October 30, 2012
    Assignees: ASMO Co., Ltd., Hitachi Cable, Ltd.
    Inventors: Ryousuke Sakamaki, Akihiro Tanba, Takashi Aoyama, Akio Hattori, Teruji Sato, Tatsuya Ohtaka
  • Patent number: 8299536
    Abstract: A semiconductor device with integrated MIS field-effect transistors includes a first transistor including a first gate electrode having a composition represented by MAx, and a second transistor including a second gate electrode having a composition represented by MAy, in which M includes at least one metal element selected from the group consisting of W, Mo, Ni, Pt, Ta, Pd, Co, and Ti, A includes at least one of silicon and germanium, and 0<x?3, and 0<y?3, and x and y are different from each other.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: October 30, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Takeo Matsuki
  • Patent number: 8301870
    Abstract: A method and structure for an out-of-order processor executing at least two threads of instructions that communicate and synchronize with each other. The synchronization is achieved by monitoring addresses of instructions in at least one of the threads.
    Type: Grant
    Filed: July 27, 2006
    Date of Patent: October 30, 2012
    Assignee: International Business Machines Corporation
    Inventor: Krishnan Kunjunny Kailas
  • Patent number: 8297079
    Abstract: The method of manufacturing porous glass base material for optical fiber includes that flame-hydrolyzing raw materials for glass in oxyhydrogen flame, depositing the generated glass fine particles on a rotating target to form porous glass base material, dehydrating and sintering the porous glass base material to transform into clear glass. The method features, in terms of the surface temperature of said porous glass base material, which changes as the burner used for depositing glass fine particle is moved relatively to said target, the temperature difference between the surface temperature of the porous glass base material touching the burner flame Ta and the surface temperature of the porous glass base material before touching the flame Tb, that is Ta?Tb, is adjusted to be within the range from 200 to 700 degrees centigrade.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: October 30, 2012
    Assignee: Shin-Etsu Chemical Co., Ltd.
    Inventor: Hiroshi Machida
  • Patent number: 8300484
    Abstract: A semiconductor device comprises a memory cell array including memory cells, a first bit line transmitting data stored in a selected memory cells, a single-ended first sense amplifier amplifying a signal voltage of the first bit line and converting the voltage into an output current, a second bit line selectively connected to the first bit line via the first sense amplifier, a second sense amplifier determining a level of the signal voltage, and a sense amplifier control circuit detecting a temperature of the memory cell array during an operation and controlling an end of an activation period of the first and/or second sense amplifiers in accordance with a detection result of the temperature. In the semiconductor device, the sense amplifier control circuit controls to delay the end of the activation period at least at a predetermined high temperature indicated by the detection result relative to at an ordinary temperature.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: October 30, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Soichiro Yoshida
  • Patent number: 8297939
    Abstract: A method of pumping an agglomerative liquid includes providing a diaphragm pump defined herein and pumping the agglomerative liquid using the diaphragm pump, the diaphragm has an annular thickened portion in the peripheral portion thereof as defined herein, the pump head has at least one channel communicating the inner peripheral edge of the clamping surface and the pump chamber, the diaphragm is reciprocally movable in opposite directions perpendicular to the diaphragm plane to increase and decrease the volume of the pump chamber so as to pump the liquid, the thickened portion of the diaphragm, the holding member, and the pump head are configured to satisfy the relation A<B as defined herein, and the reciprocal movement of the diaphragm is from the flat state toward the pump chamber side and from the flat state toward the side opposite to the pump chamber side.
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: October 30, 2012
    Assignee: Fujifilm Corporation
    Inventors: Kazuaki Oguma, Ryuji Abe
  • Patent number: 8297849
    Abstract: An inner ring is formed with an oil hole extending through a part between an inner ring raceway surface and an inner peripheral face thereof, and configured to force out grease, which has been supplied to an area between the inner ring raceway surface and an outer ring raceway surface, to the inner peripheral face in accordance with rolling of cylindrical rollers. The inner peripheral face of the inner ring is formed with a plurality of V-shaped inclined grooves configured to guide the grease, which has been forced out to the inner peripheral face of the inner ring through the oil hole, to opposite end portions of the inner peripheral face in an axial direction of the inner ring.
    Type: Grant
    Filed: August 8, 2008
    Date of Patent: October 30, 2012
    Assignee: JTEKT Corporation
    Inventor: Takeharu Uranishi
  • Patent number: 8300401
    Abstract: A holder of a magnetic storage apparatus is suggested that can efficiently absorb the shock when a vibration or shock is applied to the magnetic storage apparatus. A plurality of holding members (first shock absorbing material foam rubber 340 and second shock absorbing material foam rubber 350) that hold at least two corner parts of the magnetic storage apparatus 320 is included. The holding members are configured in a way that a total sum of holding power to hold one of opposite angles of the magnetic storage apparatus 320 and a total sum of holding power to hold the other of opposite angles are different. The first shock absorbing material foam rubber 340 is disposed on one of opposite angles, and the second shock absorbing material foam rubber 350 is disposed on the other of the opposite angles. The first shock absorbing material foam rubber 340 has greater hardness than the hardness of the second shock absorbing material foam rubber 350.
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: October 30, 2012
    Assignee: NEC Corporation
    Inventors: Toshinobu Ogatsu, Kenichiro Fujii
  • Patent number: 8297646
    Abstract: To provide a clip for an airbag, the pin member of which can be easily removed from a grommet by a simple operation even in a state in which a garnish is furnished. A clip 1 for an airbag includes: a grommet 10; and a pin member 20. The grommet 10 includes: a supporting hole 12 into which the pin member 20 is inserted from the surface side the back side; and an engaging portion 15 for preventing the pin member 20 from coming out from the supporting hole 12. The pin member 20 includes a pair of sidewalls 22 opposed to each other which are extended from a head portion 21 in the axial direction and inserted into a supporting hole 12 of the grommet 10 and freely, relatively moved in the axial direction with respect to the grommet 10.
    Type: Grant
    Filed: October 15, 2008
    Date of Patent: October 30, 2012
    Assignee: Piolax Inc.
    Inventor: Ryou Aoki
  • Patent number: 8299829
    Abstract: To provide a DLL circuit incorporating a duty adjustment circuit that is independent of the frequency of a clock signal. The DLL circuit includes: a delay line that delays a first internal clock signal to generate a second internal clock signal; a counter circuit that specifies an amount of delay of the delay line; a counter control circuit that adjusts a count value of the counter circuit; and a subtraction circuit that determines a difference between first and second count values at which the rise edge of the first internal clock signal coincides with that of a replica clock signal. The fall edge of the second internal clock signal is adjusted based on a value equivalent to one-half of the difference obtained. This prevents the applicable frequency range from being limited as with a type of duty adjustment circuit that alternately discharges capacitors.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: October 30, 2012
    Assignee: Elpida Memory, Inc.
    Inventor: Katsuhiro Kitagawa
  • Patent number: 8300991
    Abstract: Provided is a traveling-wave type semiconductor optical phase modulator capable of high speed and low voltage operation by improving an n-SI-i-n-type layered structure. A first exemplary aspect of the present invention is a waveguide-type semiconductor optical modulator including: a semiconductor substrate (101); a first n-type cladding layer (103) and a second n-type cladding layer (108) formed on the semiconductor substrate (101); an undoped optical waveguide core layer (104) and an electron trapping layer (107) formed between the first n-type cladding layer (103) and the second n-type cladding layer (108); and a hole supplying layer (106) formed between the undoped optical waveguide core layer (104) and the electron trapping layer (107).
    Type: Grant
    Filed: January 21, 2009
    Date of Patent: October 30, 2012
    Assignee: NEC Corporation
    Inventor: Tomoaki Kato
  • Patent number: 8296592
    Abstract: A resume signal hold circuit holds an assertion of a resume signal instructed while the circuit block is in a stand-by mode. A resume signal mask circuit is provided between the circuit block and the resume signal hold circuit, and masks the signals while the circuit block is in the stand-by mode so that no signal can be input to the circuit block. A power saving control circuit causes the resume signal hold circuit to hold the assertion of the event signal and causes the resume signal mask circuit to mask the signals while the circuit block is in a stand-by mode. The power saving control circuit also causes the resume signal hold circuit to cancel the holding of the assertion of the resume signal after the completion of the resume setting of the circuit block and cancelling of the signal masking by the resume signal mask circuit.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Tsuneki Sasaki, Shuichi Kunie, Tatsuya Kawasaki
  • Patent number: 8296588
    Abstract: Provided is a microcontroller including: a first low-voltage detection circuit to detect that a power supply voltage is equal to or lower than a first voltage value; a second low-voltage detection circuit to detect that the power supply voltage is equal to or lower than a second voltage value, the second voltage value being lower than the first voltage value; a CPU to stop operating when the first low-voltage detection circuit detects that the power supply voltage is equal to or lower than the first voltage value; and a real-time clock to continue operating unless the second low-voltage detection circuit detects that the power supply voltage is equal to or lower than the second voltage value, in which the first low-voltage detection circuit, the second low-voltage detection circuit, the CPU, and the real-time clock are formed on a single chip.
    Type: Grant
    Filed: July 10, 2008
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Masataka Nakano
  • Patent number: 8293153
    Abstract: A rotary powder compression molding machine according to the invention includes: a flame; a rotary shaft; a turret; a plurality of die; an upper and a lower punches; an upper and a lower rolls; a designator for designating a molding portion constituted of a set of the die and the upper and lower punches corresponding to the die; a position detector for detecting that the molding portion designated by the designator has reached a predetermined position; a separator for separating a designated molded article ejected from the molding portion designated by the designator from collection of molded articles other than the designated molded article based on a position detection signal output from the position detector; and an actuation verifier for verifying actuation of the separator based on movement of the designated molded article.
    Type: Grant
    Filed: March 31, 2010
    Date of Patent: October 23, 2012
    Assignee: Kikusui Seisakusho Ltd.
    Inventor: Masatsugu Isozumi
  • Patent number: 8294652
    Abstract: A driving method for driving an LCD panel having a counter electrode and a source line. In a first period, the counter electrode is driven to a potential VCOMH. In a second period, the counter electrode and the source line are short-circuited to a power supply interconnection having a power supply potential VCI. In a third period, the counter electrode is connected to a ground interconnection while the source line is kept to be short-circuited to the power supply interconnection. In a fourth period, the counter electrode is pulled down to a potential VCOML lower than a ground potential In a fifth period, the source line is driven to a potential corresponding to an image data while the counter electrode is kept to the potential VCOML. The electric power consumed in pulling down the counter electrode from a positive potential to a negative potential can be effectively reduced.
    Type: Grant
    Filed: October 30, 2008
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroaki Shirai
  • Patent number: 8295828
    Abstract: A first mobile terminal forming a mobile communication system connects to a base station by using a first wireless communication method (for example, GSM method). Further, a second mobile terminal acquires unique information of the base station (for example, cell information) from the first mobile terminal by communication with the first mobile terminal by using a second wireless communication method (for example, wireless LAN method), and searches a transmission frequency of the base station included in the unique information.
    Type: Grant
    Filed: April 5, 2010
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Masashi Masaki
  • Patent number: 8293637
    Abstract: A method of manufacturing a semiconductor device, includes burying a conductive pattern in an insulating film made of SiOH, SiCOH or organic polymer, treating surfaces of the insulating film and the conductive pattern with plasma which includes a hydrocarbon gas as a treatment gas, and forming a diffusion barrier film, which is formed of an SiCH film, an SiCHN film, an SiCHO film or an SiCHON film, over the insulating film and the conductive pattern with performing a plasma CVD by adding an Si-containing gas to the treatment gas while increasing the addition amount gradually or in a step-by-step manner.
    Type: Grant
    Filed: April 27, 2011
    Date of Patent: October 23, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: D669693
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: October 30, 2012
    Inventors: Dag Göranson, Örjan Göranson