Abstract: A method (and structure) of executing a matrix operation, includes, for a matrix A, separating the matrix A into blocks, each block having a size p-by-q. The blocks of size p-by-q are then stored in a cache or memory in at least one of the two following ways. The elements in at least one of the blocks is stored in a format in which elements of the block occupy a location different from an original location in the block, and/or the blocks of size p-by-q are stored in a format in which at least one block occupies a position different relative to its original position in the matrix A.

Abstract: This invention provides a one-way clutch capable of hindering the generation of a coating between each sprag and each of inner and outer rings thereby preventing sprags and inner and outer rings from being damaged due to the slip therebetween and thereby lengthening the life of the engagement between each sprag and each of the inner and outer rings. The difference in surface hardness between each sprag (4) and each of an inner ring (2) and an outer ring (3) is set to be larger than a hardness of Rockwell C-scale HRC0 and to be equal to or smaller than HRC15.

Abstract: A communication device includes a transmission signal processing unit, a driver amplifier coupled to the transmission signal processing unit, a selector coupled to the driver amplifier, a first attenuator coupled to the selector and an output portion of the communication device, a second attenuator coupled to the selector and the output portion of the communication device, and a controller coupled to the selector and the driver amplifier to switch between the first attenuator and the second attenuator based on a notification signal.

Abstract: A method that achieves convergence of a hold time error in a relatively easy way without causing a setup time error even when the hold time error occurs in a large circuit, a device and a computer-readable storage medium storing a program therefor are provided. Group a first error path and a second error path in error paths which a hold time error occurs if there is a sharing path that shares its start point with the first error path and also shares its end point with the second error path, and insert a delay element without causing a setup time error per the grouped error paths. Convergence of a hold time error can be achieved without taking into account of a node that is not included in the group and there is no worry about causing a setup time error in a path that is not included in the group.

Abstract: A device for controlling a power transmission device for a vehicle, which, at the time of gearshift, so controls the engine as to rotate at a target rotational speed, wherein at the time of shifting the gear up, a target value properly corresponding to an actual vehicle speed is set to quickly increase the engine output and to shorten the time for shifting the gear. In controlling the engine at the time of shifting the gear up, a target engine rotational speed is set based the signals from, wheel rotational speed detector means that detects the rotational speed of a wheel, such as an anti-lock control device. Thus, the target engine rotational speed is set depending properly upon an actual vehicle speed that varies accompanying an increase in the amount of engaging the clutch at the time of gearshift, and the gear at the time of accelerating the vehicle can be quickly shifted up without accompanied by the shift shock.

Abstract: A microcomputer includes a CPU, a protection information storage configured to store memory protection information specifying an access permission or prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information and a reset apparatus configured to invalidate the memory protection information stored in the protection information storage according to a reset request signal output from the CPU.

Abstract: A flat cable includes a plurality of conductors arranged in parallel and exposed at both end portions in a longitudinal direction thereof, an insulation film covering the plurality of conductors except the exposed both end portions, and a reinforcing member that covers the plurality of conductors along a width direction of the plurality of conductors, is provided on a surface of the insulation film in a part of a region including an edge of the insulation film, and includes a metal plate and an insulative covering layer for covering the metal plate.

Abstract: By more flexibly controlling connection for each transmission rate in the wireless base station, the connection is established using possibly a higher transmission rate so long as the connection capacity of the wireless base station has a margin while efficiently determining the transmission rate according to the wave intensity from a wireless communication terminal. If the connection capacity of the base station has a margin after additionally connecting one wireless communication terminal, i.e., if the communication traffic is equal to or less than a predetermined margin threshold value, the rate decision threshold value to determine the transmission rate for connection is lowered by a predetermined value to determine a transmission rate so that the connection is established using a transmission rate higher than that determined by the rate decision threshold value as the default value (initial value) to thereafter establish the connection.

Abstract: In a layout pattern generating method, a specific rework cell used for edition is specified among rework cells and fill cells which are arranged in a semiconductor chip area and a specific pattern of a predetermined shape is generated in a wiring layer for the specific rework cell. A dummy wiring pattern is arranged in at least a part of the wiring layer of and the fill cell and un-specific rework cells among the rework cell other than the specific rework cell. The specific pattern is deleted from the wiring layer for the specifying rework cell. A wiring pattern is arranged in the wiring layer for the specific rework cell by wiring the specific rework cell as a logic cell.

Abstract: A semiconductor device including a plurality of memory cells arranged in a matrix pattern, a write amplifier which writes write data to the memory cell in synchronization with a clock, a sense amplifier which reads out the write data written in the memory cell in synchronization with the clock, a plurality of column select switches which connect the plurality of the memory cells with the sense amplifier and the write amplifier, a column address decoder which makes the column select switch corresponding to one column among the plurality of the memory cells a conductive state based on a column address, a row address decoder which activates the memory cell of one row based on a row address, and a test write circuit which writes data corresponding to a logical level of a test signal to the memory cell based on a test mode signal.

Abstract: An interconnect substrate is placed over a first inductor of a semiconductor chip and a second inductor of another semiconductor chip. The interconnect substrate includes a third inductor and a fourth inductor. The third inductor is located above the first inductor. The distance from the first inductor to the third inductor is longer than the distance from the second inductor to the fourth inductor.

Abstract: A random number generator includes a fairness checker and correction module that ensures that a complete random sequence within a predetermined period of time will be output by the random number generator.

Abstract: Disclosed is a semiconductor device including a mode control circuit that, when a standby control signal is in an activated state, based on a timer output signal from a timer circuit, generates a MODE control output signal that changes a logic state of a functional circuit part at every prescribed time interval, and an output control circuit that receives an output signal of the functional circuit part and controls output of the output signal; based on a delay output signal generated by delaying a MODE control output signal by a delay circuit. While the functional circuit part is changing the logic state by the MODE control output signal, the output control circuit does not transfer the functional circuit part output signal to output, but holds and outputs a functional circuit part output signal immediately before the functional circuit part changes the logic state by the MODE control output signal.

Abstract: A switching hub for processing a VLAN frame transmitted through a transmission line of a ring network includes two ring ports connected to the transmission line of the ring network, and a forwarding processing mechanism for, when one of the two ring ports receives the frame and when a VLAN in which the received frame belongs is a VLAN only through both the ring ports, forwarding the frame to the other ring port without performing FDB learning on the frame.

Abstract: An insulated wire includes a conductor, and an insulating layer of a porous member formed on the conductor by using a water-in-oil type emulsion (W/O emulsion) including a thermosetting liquid solventless varnish as the oil and water drops of water-soluble polymer contained in the thermosetting liquid solventless varnish as the water. The insulating layer of the porous member is formed by that the water-in-oil type emulsion is coated so as to form a thin film as a coated film, the thermosetting liquid solventless varnish as the oil is polymerized and cured after the formation of the thin film, and the water drops as the water is dried and removed after the curing of the thermosetting liquid solventless varnish.

Abstract: A driver includes a plurality of output portions; and an output switching control portion. The plurality of output portions is synchronized with a shift pulse signal. The shift pulse signal indicates one specification shift pulse signal among a plurality of specification shift pulse signals. The plurality of specification shift pulse signals indicates a plurality of output numbers which are different from each other based on respective specifications of the plurality of specification shift pulse signals. The one specification shift pulse signal indicates a setting output number as one output number among the plurality of output numbers. The output switching control portion selects a group of output portions corresponding to the setting output number among the plurality of output portions based on the one specification shift pulse signal.

Abstract: A semiconductor apparatus capable of detecting a crack generated in a semiconductor chip while the design freedom, the layout freedom of a wiring, the layout efficiency of LSI, and the layout efficiency of a package substrate are improved. The semiconductor apparatus according to the invention includes a semiconductor chip having a multilayered wiring structure; plural electrode pads being formed on a top surface along the outer periphery of the semiconductor chip; and a wiring being coupled to a first electrode pad and a second electrode pad selected from the plural electrode pads and formed along the entire outer periphery of the semiconductor chip in plan view. The wiring includes a first wiring and a second wiring that are formed on different layers, and the first wiring and the second wiring are connected in series by a connection plug.

Abstract: An operational amplifier circuit includes: an input differential stage circuit supplied with power supply voltages in a first voltage range; and an output stage circuit supplied with power supply voltages in a second voltage range which is different from the first voltage range. The operational amplifier circuit amplifies a signal supplied to the input differential stage circuit and outputs the amplified signal from the output stage circuit to drive a load.

Abstract: Sharpness is calculated in all of focus-bracketed images on a pixel basis. Then, a first reference value indicating an image of the plurality of images to which a pixel whose sharpness is the highest among the pixels located on the identical positions in the plurality of images belongs is obtained on each pixel of the images, and a second reference value is calculated based on the first reference value on each pixel by spatially smoothing the first reference value on each pixel based on the first reference values on adjacent pixels. The focus-bracketed images are processed based on the second reference values to generate an omni-focus image or a blur-enhanced image. Accordingly, it is possible to judge a region having high contrast as an in-focus region and acquire a synthesized image having smooth gradation.