Patents Represented by Attorney McGinn IP Law Groups PLLC
  • Patent number: 8277257
    Abstract: A connector connectable to a plurality of receptacles of different specifications is provided while a connector of the prior-art configuration is not adapted for the connection with such receptacles. The connector includes: a connector body; and a connector portion partially inserted in the connector body and partially projected from the connector body. The connector portion includes: a first connector block that is singularly capable of mating with a receptacle conforming to a first specification but is singularly incapable of mating with a receptacle conforming to a second specification; and a second connector block that is disposed on the first connector block and combined with the first connector block to be capable of mating with the receptacle conforming to the second specification. The second connector block is free to slide on the first connector block 21 and to be inserted in the connector body.
    Type: Grant
    Filed: February 14, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yutaka Noguchi
  • Patent number: 8279672
    Abstract: A nonvolatile memory includes memory blocks each including a data storage area for storing user data and a discrimination area that is provided so as to correspond to the each data storage area on a one-to-one basis and stores discriminative data indicating a writing state of data to the data storage area. The nonvolatile memory further includes a control circuit which determines the data storage area that will be a storage destination of the user data based on a relative difference relation among the discriminative data of the respective memory blocks, and changes the discriminative data of the discrimination area corresponding to the data storage area in which the user data was written to a value different from that before the writing.
    Type: Grant
    Filed: January 20, 2010
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kaori Oba
  • Patent number: 8281277
    Abstract: Signal selecting apparatus 100 according to the present invention for determining an operation parameter of circuit 101 includes circuit analyzing means 110 for enumerating signals in the circuit that are to be measured for the operation parameter when information of the circuit is input thereto, observation signal number determination means 111 for statistically determining the number of observation signals required to determine the operation parameter from the width and reliability of an estimated error and from the number of enumerated signals, and observation signal selecting means 112 for selecting, from the enumerated signals, the same number of signals as the number of observation signals.
    Type: Grant
    Filed: September 25, 2007
    Date of Patent: October 2, 2012
    Assignee: NEC Corporation
    Inventor: Kohei Hosokawa
  • Patent number: 8279303
    Abstract: An exposure control unit 15 controls a charge accumulation time for a CMOS sensor 10. The CMOS sensor 10 captures an image P1 with a charge accumulation time T1 and an image P2 with a charge accumulation time T2. The charge accumulation time T1 does not cause a flicker in an image under a light source blinking at a first blink cycle. The charge accumulation time T2 is different from the charge accumulation time T1. A difference image generation unit 17 generates a difference image DP that emphasizes to show a difference in luminance of the images P1 and P2. A flicker detection unit 18 detects a flicker occurrence in the image P2 based on a difference in luminance between P1 and P2 appearing in the difference image DP.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Kentarou Niikura
  • Patent number: 8281221
    Abstract: An operation method of a MRAM of the present invention stores in memory arrays, error correction codes, each of which comprises of symbols, each of which comprises bits, and to which an error correction is possible in units of symbols. In the operation method, the symbols are read by using the reference cells different from each other. Moreover, when a correctable error is detected in a read data of the error correction code from data cells corresponding to an input address, (A) a data in the data cell corresponding to an error bit is corrected, for a first error symbol as an error pattern of one bit, and (B) a data in the reference cell that is used to read a second error symbol is corrected for a second error symbol as en error pattern of the bits.
    Type: Grant
    Filed: October 17, 2006
    Date of Patent: October 2, 2012
    Assignee: NEC Corporation
    Inventors: Noboru Sakimura, Takeshi Honda, Tadahiko Sugibayashi
  • Patent number: 8278143
    Abstract: A manufacturing method for an electronic device joining a first metallic bond part formed on a first electronic component and a second metallic bond part formed on a second electronic component includes a first process for placing the first metallic bond part directly against the second metallic bond part, applying pressure to the first electronic component and the second electronic component, joining the first metallic bond part to the second metallic bond part with solid-phase diffusion, and releasing the applied pressure, and a second process for heating the first electronic component and the second electronic component at a predetermined temperature such that the first metallic bond part and the second metallic bond part are joined together by melting at least one of the first metallic bond part and the second metallic bond part.
    Type: Grant
    Filed: June 22, 2011
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoichiro Kurita
  • Patent number: 8279917
    Abstract: A pulse width modulation (PWM) controller includes: a first counter for counting a reference clock signal, and thus outputting a first count value, a leading edge control signal generator for outputting a leading edge control signal on a basis of the first count value, an adjustment clock generator for generating an adjustment clock signal, a second counter controller for instructing the adjustment clock generator to start to output the adjustment clock signal, a second counter for outputting a second count value, a trailing edge control signal generator for outputting a trailing edge control signal on a basis of the second count value, and a PWM pulse generator for synthesizing the leading edge control signal and the trailing edge control signal, and thus generating a pulse width modulation signal.
    Type: Grant
    Filed: May 15, 2009
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hideyuki Takahashi
  • Patent number: 8277051
    Abstract: An apparatus includes a lamp a power supply for supplying power to lamp, an image processing unit for displaying an image according to any one of a plurality of video signals applied externally, and a control unit for causing the power supply to start supplying power to the lamp when at least one of the plurality of video signals is applied in an initial state, checking whether or not any one of the plurality of video signals is applied within a predetermined period of time from the time when the applied video signal is stopped, making the power supply continue to supply power to the lamp if at least one of the plurality of video signals is applied, and making the power supply stop supplying power to the lamp if any one of the plurality of video signals has not been applied.
    Type: Grant
    Filed: May 15, 2008
    Date of Patent: October 2, 2012
    Assignee: Nec Display Solutions, Ltd.
    Inventors: Daisuke Moriwaki, Koichi Ara, Michio Tomizawa
  • Patent number: 8279230
    Abstract: A display device is provided with a display panel; and a display panel driver driving the display panel in response to externally-provided image data. The display panel driver includes a display memory for storing the image data, and is configured to perform overdrive processing on the image data read from the display memory. The display panel driver includes an overdrive processing control circuit detecting writing of the image data into the display memory to control operation and halt of a circuit used for the overdrive processing.
    Type: Grant
    Filed: May 27, 2009
    Date of Patent: October 2, 2012
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Nose, Hirobumi Furihata
  • Patent number: 8278998
    Abstract: A power supply noise reduction circuit and a power supply noise reduction method for reducing power supply noise at any frequency, includes forcing a power supply noise to resonate to the resonance frequency of a parallel resonance circuit, including an inductor and a capacitor to set the frequency of the noise equal or close to the resonance frequency of the parallel resonance circuit and, attenuating the noise, set equal or close to the resonance frequency of the parallel resonance circuit, using a low-pass filter including a resistor and a capacitor.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: October 2, 2012
    Assignee: NEC Corporation
    Inventor: Mikihiro Kajita
  • Patent number: 8280139
    Abstract: A cell feature amount calculating apparatus is provided that is capable of capturing the state of nuclear DNA. This cell feature amount calculating apparatus includes an image input unit that inputs an image of a cell, a cell nucleus region extracting unit that extracts a cell nucleus region of the cell from the image, a standard contour length calculating unit that calculates a standard contour length of the cell nucleus region, a contour length sequence calculating unit that extracts, for each threshold value of a plurality of different threshold values, a specific region which is a region having a pixel value larger than or equal to the threshold value from the cell nucleus region and calculating a contour length sequence by calculating a contour length of the specific region, and a contour complexity calculating unit that calculates a feature amount of the cell based on the standard contour length and the contour length sequence.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: October 2, 2012
    Assignee: NEC Corporation
    Inventor: Tomoharu Kiyuna
  • Patent number: 8275957
    Abstract: A method (and system) of storing data in a value-based storage system, includes optimizing a value of data stored in the value-based storage system.
    Type: Grant
    Filed: April 3, 2008
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Nikhil Bansal, Frederick Douglis, Lisa Karen Fleischer, Kirsten Weale Hildrum, Akshay Kumar Reddy Katta, John Davis Palmer, Elizabeth Suzanne Richards, David Tao, William Harold Tetzlaff, Joel Leonard Wolf, Philip Shi-lung Yu
  • Patent number: 8274155
    Abstract: An interconnect is provided in a first insulating layer and the upper surface of the interconnect is higher than the upper surface of the first insulating layer. An air gap is disposed between the interconnect and the first insulating layer. An etching stopper film is formed over the first insulating layer, the air gap, and the interconnect. A second insulating layer is formed over the etching stopper film. A via is provided in the second insulating layer and is connected to the interconnect. A portion of the etching stopper film that is disposed over the air gap is thicker than another portion that is disposed over the interconnect.
    Type: Grant
    Filed: April 12, 2010
    Date of Patent: September 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Tatsuya Usami
  • Patent number: 8274166
    Abstract: A semiconductor device includes a substrate; an alignment mark formed on the substrate and composed of a metal film; a cover insulating film formed on the alignment mark and covering an entire surface of the alignment mark; and a polyimide film formed on the cover insulating film, and having an opening, which is opened on the alignment mark and has an end face aligning with an end face of the alignment mark, in plan view.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hirokazu Shimada
  • Patent number: 8273665
    Abstract: A method of making a nanoparticle array that includes replicating a dimension of a self-assembled film into a dielectric film, to form a porous dielectric film, conformally depositing a material over said porous dielectric film, and anisotropically and selectively etching said deposited material.
    Type: Grant
    Filed: August 20, 2009
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Charles T. Black, Kathryn Wilder Guarini
  • Patent number: 8272886
    Abstract: A connector capable of being water-tightly secured to cables without locally applying pressure to the cables is provided. A male connector 14 is formed with at least one guide groove 18m extending in an insertion direction on a portion in a circumferential direction, a female connector 16 is formed with at least one guide protrusion 20m that extends in the insertion direction and can be inserted into the guide groove 18m corresponding to the guide groove 18m, the guide protrusion 20m has both ends coupled to an outer surface of the second connector 16, a middle portion of the guide protrusion 20m is formed to be an elastic arm separated from the outer surface, and a lock mechanism is provided between the guide groove 18m and the guide protrusion 20m.
    Type: Grant
    Filed: November 13, 2009
    Date of Patent: September 25, 2012
    Assignee: Join Co., Ltd.
    Inventor: Syogo Seido
  • Patent number: 8275000
    Abstract: A wireless communication system includes a base station and a terminal station. The base station extracts paths that have a power level that exceeds a predetermined threshold value from delay profiles of the terminal station as available paths, selects a path having a maximum power or a first path from the available paths as a reference path, calculates a time difference between an arrival time of the reference path and a predetermined maximum arrival time, and transmits a result to the terminal station as a transmission timing control signal. The terminal station adjusts the transmission timing to the base station according to the time difference. The base station transmits the transmission timing control signal only when the base station detects the reference path.
    Type: Grant
    Filed: June 9, 2008
    Date of Patent: September 25, 2012
    Assignee: NEC Corporation
    Inventors: Shingo Kikuchi, Motoya Iwasaki
  • Patent number: 8275555
    Abstract: A method and system for representing a similarity between at least two genomes that includes detecting gene clusters which are common to the at least two genomes and representing the common gene clusters in a PQ tree. The PQ tree includes a first internal node (P node), that allows permutation of the children thereof, and a second internal node (Q node), that maintains unidirectional order of the children thereof.
    Type: Grant
    Filed: January 7, 2011
    Date of Patent: September 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Gad M. Landau, Laxmi Priya Parida, Oren Weimann
  • Patent number: 8274468
    Abstract: A flat panel display includes first and second signal drivers which drive a first and second group signal lines of a display panel in accordance with an input first and second group video data respectively. A controller controls a timing of sending the first group video data to the first signal driver via the first data line, and a timing of sending the second group video data to the second signal driver via the second data line. A delay time generating section shifts a relative timing between a timing at which the first signal driver receives the first group video data and a timing at which the second signal driver receives the second video data by a determined time. The problem of the deterioration of the EMI caused by synchronization of the peak currents respectively generated in signal drivers for driving a flat panel display can be suppressed.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: September 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Yoshihiko Hori
  • Patent number: 8274504
    Abstract: Disclosed is an output amplifier circuit including a differential stage, a first output stage that receives outputs of the differential stage, and a second output stage having an output thereof electrically connected to a load. The differential stage receives an input signal at a non-inverting input thereof. In the first connection configuration, an output of the first output stage is electrically disconnected from the output of the second output stage, outputs of the differential stage are electrically disconnected from inputs of the second output stage, and a second input of the differential stage is electrically connected to the output of the first output stage. In the second connection configuration, the output of the first output stage is electrically connected to the output of the second output stage, and the outputs of the differential stage is electrically connected to the inputs of the second output stage.
    Type: Grant
    Filed: March 30, 2009
    Date of Patent: September 25, 2012
    Assignee: Renesas Electronics Corporation
    Inventor: Hiroshi Tsuchi