Abstract: An adaptive equalizer includes: an adaptive filter; and a control unit. The adaptive filter performs an adaptive equalization processing for an input signal modulated by a modulation method that produces a modulation signal with constant amplitude characteristics so as to make an amplitude of an equalized output signal constant. The control unit controls stop and execution of the adaptive equalization processing of the adaptive filter in accordance with characteristics of at least one of the input signal and the output signal.

Abstract: A steering apparatus includes a fixed bracket, an outer column, an arm unit, an inner column, a steering shaft, and a tightening tool. The outer column includes a main holding body portion, a divided portion, and a tightening portion. The arm unit includes by a bifurcated arm portion that extends axially outward in a substantially bifurcated shape at the axial front side of the main holding body portion and a linking portion formed between the arms of the bifurcated arm portion. The inner column is held by the outer column. The steering shaft is pivotally supported by the linking portion. Two tightening plate pieces of the tightening portion are disposed inside two fixed side portions of the fixed bracket and tightenably connected by the tightening tool.

Abstract: A semiconductor memory device includes an I/O line for transmitting read data that has been read from a memory cell, a plurality of driver circuits for driving the I/O line on the basis of the read data, a read circuit for receiving the read data transmitted through the I/O line, and an assist circuit for amplifying the read data transmitted through the I/O line. The assist circuit is disposed farther away from a prescribed drive circuit included in the plurality of drive circuits as viewed from the read circuit. The signal level can thereby rapidly change levels even in memories having relatively long I/O lines.

Abstract: A manufacturing method of a semiconductor device includes: forming a wiring in a first interlayer insulating layer in a first region; etching an surface portion of the first interlayer insulating layer in a second region; forming a plurality of opening portions extended below in the etched region; and forming a lower electrode layer, a dielectric layer, and a common upper electrode in each of the plurality of opening portions to form a plurality of capacitance portions. The step of forming the plurality of capacitance portions, includes: forming the common upper electrode so that an upper surface of the first interlayer insulating layer and an upper surface of the common upper electrode approximately lie in the same plane.

Abstract: Provided is a light receiving circuit including: a photodiode; a first amplifier including a feedback resistor connected between an input and an output of an inverting amplifier and having an input connected to a cathode of the photodiode; a second amplifier having a configuration similar to that of the first amplifier and having an input connected to an anode of the photodiode; a capacitor element connected between an output of the first amplifier and the input of the second amplifier; and a bias current control circuit that outputs a bias current to the input of the second amplifier according to a current value of the photocurrent, and controls an output voltage signal of the light receiving circuit according to an output of the second amplifier by using the bias current to adjust the sensitivity. The bias current control circuit changes the sensitivity according to the output of the second amplifier.

Abstract: A state transition management device includes a memory that stores subsequent state number candidates for a current state number and a selection circuit that selects a subsequent state number from among the subsequent state number candidates that have been read out from the memory. For the state number having the subsequent state number candidates that are branch destinations of the current state number and are small in number, the memory stores the subsequent state number candidates for a plurality of current state numbers at one address in the memory that can be concurrently read out. The selection circuit selects the subsequent state number based on an event identification code (109, 110) and a current state number.

Abstract: A network relay device is for receiving, from an external network relay device, connection confirmation information indicative of being in communication connection with the external network relay device. When the connection confirmation information is particular connection confirmation information indicative of being transmitted from a predetermined external network relay device, the network relay device provides return confirmation information to the predetermined external network relay device.

Abstract: A plasma display panel equipped with a front substrate and a back substrate facing each other to form a discharge space. On the discharge space side of the front substrate there are disposed a metal oxide layer and magnesium oxide crystal particles. Among the magnesium oxide crystal particles there are magnesium oxide crystal particles having a particle diameter of at least 3500 angstroms.

Abstract: A semiconductor device includes a gate stack structure. The gate stack structure includes an interfacial layer formed on a semiconductor substrate, a high-k dielectric formed on the interfacial layer, a silicide gate including a diffusive material and an impurity metal, and formed over the high-k dielectric, and a barrier metal with a barrier effect to the diffusive material, and formed between the high-k dielectric and the metal gate. The impurity metal has a barrier effect to the diffusive material so that the diffusive material in the silicide gate can be prevented from being introduced into the high-k dielectric.

Abstract: A plasma display panel equipped with a front substrate and a back substrate facing each other to form a discharge space. On the discharge space side of the front substrate there are disposed a metal oxide layer and magnesium oxide crystal particles. The magnesium oxide crystal particles are arranged on the discharge space side of the metal oxide layer, or alternatively, part of the magnesium oxide crystal particles are disposed within the metal oxide layer.

Abstract: A solar cell lead wire includes a conductive material, and a solder plated layer on a periphery of the conductive material. The solder plated layer is formed flat by rolling. A method of manufacturing a solar cell lead wire includes feeding an elongate conductive material from a feed reel, the elongate conductive material including a rectangular conductor or a round conductor, soaking the conductive material in a molten solder in a molten solder plating bath, cooling the conductive material to have a plated wire with a solder plated layer formed on the conductive material, and winding the plated wire on a winding reel. The plated wire is formed flat by rolling after the solder plated layer of the plated wire is solidified by the cooling.

Abstract: In accordance with one embodiment of the invention, a display control device includes a driving circuit driving pixels based on successively inputted display data; and a drive mode control circuit determining an operation mode of the driving circuit based on the difference value between first display data among the display data and second display data among the display data, the first display data being the (N+1)th display data, and the second display data being the Nth display data.

Abstract: A video signal selector has a selector switch for selectively outputting one of an endoscopic video signal and an ultrasonic video signal, and a selector control circuit for controlling the selector switch. The selector switch selects the endoscopic video signal by default. The selector control circuit switches the selector switch to the ultrasonic video signal in response to input of an ultrasonic image capture command for commanding to save an ultrasonic image.

Abstract: A plurality of vias is disposed side by side on a multilayer board. A first via which is one of the vias disposed at one outer portion is electrically connected to a first outgoing line provided on the multilayer board. A second via at the other outer portion is electrically connected to a second outgoing line provided on the multilayer board. A plurality of the vias is connected to a first fixed potential layer (a ground layer, for example) of the multilayer board. At least one second fixed potential layer is provided, with a plurality of the vias through a clearance and having the same potential as that of the first fixed potential layer, as an inner layer of the multilayer board between the first and second outgoing lines and the fixed potential layer. Therefore, a BPF whose rate of occupied area is low is formed on the multilayer board without additional production processes.

Abstract: Pulse detection portion detects pulses in a horizontal synchronization signal and acquires the occurrence period and the pulse width of the detected pulses. Synchronization pulse decision portion determines pulses, for which the differences between the occurrence period and the reference period and between the pulse width and the reference pulse width are within their respective error tolerance ranges, as synchronization pulses. Mean period acquisition portion obtains the mean period by averaging occurrence periods of the synchronization pulses. Reference period correction portion carries out either or both of correcting the reference period so as to get closer to the mean period and correcting the error tolerance range of the reference period so as to get narrower, under the condition that the occurrence frequency of the synchronization pulses for which the difference between the occurrence period and the mean period is outside of a predetermined tolerance range exceeds a predetermined threshold.

Abstract: An impedance measurement method for circuits that has multiple power supply ports and a common ground shared by the multiple power supply ports, that includes finding multiple mutual impedances; finding approximate values for the ground impedance from the multiple mutual impedances; calculating multiple power supply port impedances from the approximate ground impedance values; and generating an equivalent circuit for the applicable circuit based on the ground impedances.

Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.

Abstract: A microcomputer that controls an ultrasonic motor includes a storage unit that stores a compare register value, and a digital/analog (D/A) conversion set value, a D/A converter that generates an amplitude control signal with an amplitude value corresponding to the D/A conversion set value, a timer that generates a pulse width modulation (PWM) signal with a frequency corresponding to the compare register value, a central processing unit (CPU) that reads the D/A conversion set value, and the compare register value from the storage unit, and that sets the D/A conversion set value and the compare register value to the D/A converter and the timer, respectively, and an output circuit that generates the control signal with the amplitude of the amplitude control signal, and the frequency of the PWM signal, in response to the amplitude control signal and the PWM signal.

Abstract: An output circuit includes a first differential pair of transistors driven by a first current source and differentially receiving input signals and a second differential pair of transistors driven by a second current source and differentially receiving first control signals (EMT, EMB). Output pairs of the first and second differential pairs are connected to the differential output terminals. A load resistor element pair is connected between a power supply and the differential output terminals. The output circuit further includes a third differential pair of transistors driven by a third current source and differentially receiving second control signals and a fourth differential pair of transistors driven by a fourth current source and differentially receiving third control signals. An output pair of the third differential pair of transistors is connected between one of the differential output terminals and the power supply.

Abstract: To include a first memory cell array area and a second memory cell array area, a peripheral circuit area arranged between these memory cell array areas, a first pad row arranged between the first memory cell array area and the peripheral circuit area, and a second pad row arranged between the second memory cell array area and the peripheral circuit area. No peripheral circuit is arranged substantially between the first memory cell array area and the first pad row as well as between the second memory cell array area and the second pad row. With this arrangement, a memory cell array area and a predetermined pad can be connected within a shorter distance by using a wiring formed in an upper layer that has a lower electrical resistance, and a power potential can be stably supplied to the memory cell array area.