Abstract: A method of testing a relay set which includes mapping a relay set to an undirected graph indicative of a topology of the relay set and includes vertices indicative of channels of the relay set and edges extending between corresponding vertices indicative of relays. Values based on a characteristic of a relay of the relay set that corresponds to the respective edge of the undirected graph are stored. A plurality of candidate test paths for a relay-to-test that each connects a first input/output (I/O) channel and a second I/O channel, and includes the relay-to-test are identified. A total value for the edges of the candidate test paths is determined for each of the candidate test paths. The total values are compared to one another and a test path is determined for the relay-to-test based on the comparison.

Abstract: Provided is a strain gage mount, including an instrument carrier mount configured to secure a strain gage during use, a specimen mount configured to couple to a specimen during use, and a thermal insulating layer configured to be disposed between the instrument carrier mount and the specimen mount during use.

Abstract: An apparatus may include an interconnect; at least one processor coupled to the interconnect; and at least one memory controller coupled to the interconnect. The memory controller may be programmable by the processor into a loopback test mode of operation and, in the loopback test mode, the memory controller may be configured to receive a first write operation from the processor over the interconnect. The memory controller may be configured to route write data from the first write operation through a plurality of drivers and receivers connected to a plurality of data pins that are capable of connection to one or more memory modules. The memory controller may be further configured to return the write data as read data on the interconnect for a first read operation received from the processor on the interconnect.

Abstract: Method and apparatus for multi-destination pick using motes. In embodiments, each receptacle may be assigned to a destination and may have a sensor that detects when an item is placed in the receptacle to deactivate the indicator and/or to verify that the item was placed in the correct receptacle. The sensor may be coupled via a wired or wireless connection to a mote that may include a communication interface for communicating with a control system and with other motes in an ad-hoc network. In some embodiments, each mote may also include an indicator that may be activated by a control system to indicate to the agent that the receptacle is the destination receptacle for a picked item. The agent may then place the item in the indicated destination receptacle. In one embodiment, the mote on the destination receptacle may be activated when the picked item is scanned by the agent.

Abstract: To allocate resources in an orthogonal frequency domain multiple access (OFDMA) system, two-dimensional rectangular regions are assigned in a frequency-time space to data bursts associated with mobile stations. At least one data burst does not fit in an available space in the frequency-time space is determined. In response to the determining, the assigned two-dimensional rectangular regions are reshaped.

Abstract: In one embodiment, a processor comprises a core configured to execute a data cache block write instruction and an interface unit coupled to the core and to an interconnect on which the processor is configured to communicate. The core is configured to transmit a request to the interface unit in response to the data cache block write instruction. If the request is speculative, the interface unit is configured to issue a first transaction on the interconnect. On the other hand, if the request is non-speculative, the interface unit is configured to issue a second transaction on the interconnect. The second transaction is different from the first transaction. For example, the second transaction may be an invalidate transaction and the first transaction may be a probe transaction. In some embodiments, the processor may be in a system including the interconnect and one or more caching agents.

Abstract: A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining.

Abstract: A user may utilize a prototyping environment to create a sequence of motion control, machine vision, and/or data acquisition (DAQ) operations, e.g., without needing to write or construct code in any programming language. For example, the environment may provide a graphical user interface (GUI) enabling the user to develop/prototype the sequence at a high level, by selecting from and configuring a sequence of operations using the GUI. The prototyping environment application may then be operable to automatically, i.e., programmatically, generate graphical program code implementing the sequence. For example, the environment may generate a standalone graphical program operable to perform the sequence of operations.

Abstract: A system and method for efficient garbage collection. A general-purpose central processing unit (CPU) sends a garbage collection request and a first log to a special processing unit (SPU). The first log includes an address and a data size of each allocated data object stored in a heap in memory corresponding to the CPU. The SPU has a single instruction multiple data (SIMD) parallel architecture and may be a graphics processing unit (GPU). The SPU efficiently performs operations of a garbage collection algorithm due to its architecture on a local representation of the data objects stored in the memory. The SPU records a list of changes it performs to remove dead data objects and compact live data objects. This list is subsequently sent to the CPU, which performs the included operations.

Abstract: A method and apparatus for dynamic scan chain grouping is disclosed. In one embodiment, an integrated circuit (IC) includes a number of scan partitions. Each scan partition includes a number of scan input ports and a number of corresponding scan output ports. Each scan input port and each scan output port includes a number of scan paths. Additionally, each scan partition includes a number of scan chains. Each scan partition is programmable to couple the scan paths of one of the scan input ports to each of the scan chains. Similarly, the corresponding output port may also be coupled to the scan chains. The scan paths of the remaining scan input ports may be selected to bypass the scan chains of the scan partition, having their respective scan input ports connected directly to their respective scan output ports. Each scan partition may be reconfigurable.

Abstract: The invention relates to transmission from a base station to a receiver, the base station comprising first radiating means arranged for transmitting according to an antenna pattern with respect to the receiver and further comprising second radiating means arranged for transmitting according to the same antenna pattern as the first radiating means with respect to the receiver, the transmissions of the first and second radiating means being time shifted by a determined duration.

Abstract: Various embodiments of a system and method for preventing large-scale account lockout are described. The system and method for preventing large-scale account lockout may include an account access control component configured to prevent fraudulent individuals from locking access to user accounts. The account access control component may lock access to an account after a lockout threshold is tripped. To prevent an account from being locked by fraudulent individuals, the account access control component may utilize a warning threshold.

Abstract: In an embodiment, a method to automatically process modifications to a set of design files is contemplated. The design files describe at least a portion of an integrated circuit design, and may be coded in a hardware description language. The modifications may be made to prepare the design files for inclusion in a programmable logic device implementation of the integrated circuit (or portion thereof). Specifically, the modifications may be specified using a set of commands which may be assembled by a user.

Abstract: A method to find symmetries along curved paths in input scenes. The method may detect a curve in an input scene and one or more elements on that curve. The method may define and group points for the one or more element on the curve, and define a centroid for each group. The method may then parameterize a transformation in transformation space between each centroid pair in the input scene. The method may then extract transformation paths by clustering points. The method may create phantom objects in case of mirroring along curved paths to help detect the curved paths.

Abstract: A method for data storage includes predefining an order of programming a plurality of analog memory cells that are arranged in rows. The order specifies that for a given row having neighboring rows on first and second sides, the memory cells in the given row are programmed only while the memory cells in the neighboring rows on at least one of the sides are in an erased state, and that the memory cells in the given row are programmed to assume a highest programming level, which corresponds to a largest analog value among the programming levels of the cells, only after programming all the memory cells in the given row to assume the programming levels other than the highest level. Data is stored in the memory cells by programming the memory cells in accordance with the predefined order.

Abstract: A switched-capacitor circuit on a semiconductor device may include accurately matched, high-density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch.

Abstract: Disclosed is a device having a rotor that is adapted to be rotated relative to a stator, with hydrostatic bearings being used as radial bearings and as axial bearings of the rotor. A motor is provided as a direct drive, having a ring-shaped part and also a plurality of motor segments which are in magnetic engagement with the ring-shaped part. In order to generate additional bearing load force, additional motor segments having permanent magnets are provided. For reasons of safety, axial support rolls are provided which, when the motor has attained a given bearing load force, are spaced from a running face of the rotor, and which, in a case of too low or an absence of load force, prevent a displacement of the rotor away from the axial bearings.

Abstract: A system for capturing images of an object includes an image capture booth, one or more lights coupled to the image capture booth, a platter coupled to the image capture booth, and a hanger coupled to the image capture booth. The image capture booth includes panels that enclose a space for imaging objects. The lights illuminate at least a portion of the space. The platter and the hanger each support objects for imaging of the objects in the image capture booth.

Abstract: 3D scenes may be rendered a resolution lower than a resolution associated with the resultant image. A graphics application or 3D editor may render the 3D artwork at a lower resolution while the user modifies or manipulates the 3D model from which the artwork is derived. In some embodiments, an image may include multiple image layers, each representing a portion of the overall finished image. Graphics programs generally associate a target resolution with an image. Rendering 3D artwork at high resolutions may take extra time and result in poor performance. Thus, in some embodiments, a graphics program may be configured to render 3D artwork at a lower resolution than the resultant image's target or associated resolution while a user is modifying the 3D model. Subsequently, after the user has completed manipulating the 3D model, the graphics program may render the 3D model again at the image's associated resolution.

Abstract: An aging detection circuit is disclosed. An aging detection circuit may include at least an inverter and a half-latch. During a power-up sequence, if an input voltage of the first inverter changes sufficiently to cause the output of the inverter to change states, the output of the half-latch may be set to a state indicating aging of the circuit. This indication may be used in determining whether or not a supply voltage should be changed to compensate for the aging. A first transistor of the inverter may be arranged such that it remains active subsequent to power-up of the circuit. When active, the first transistor may be subject to degradation mechanisms associated with aging and which change its threshold voltage. The threshold voltage may change such that on a successive power-ups of the circuit, the first transistor is at least momentarily deactivated, leading to the setting of the state indicating aging by the half-latch circuit.