Abstract: An information processing system and method of operation are provided. In response to a first instruction, a supplemental memory stores first information from a system memory. In response to a second instruction, a cache memory stores second information from the supplemental memory if the first information includes the second information and from the system memory otherwise.

Abstract: During a first cycle, data information is output through a bus from a device coupled to the bus. During a second cycle immediately after the first cycle, address information is output through the bus from the device.

Abstract: With first semiconductor circuitry, a first signal is received having a first voltage between a voltage A and a voltage B. With second semiconductor circuitry, a second signal is output having a second voltage between a voltage C and a voltage D in response to the first signal. C is greater than A, and D is greater than B.

Abstract: A method and structure are provided for connecting to integrated circuitry. A connectivity cell includes multiple terminals formed within the integrated circuitry. The connectivity cell further includes at least one metal layer connected to at least one of the terminals. A first area is a substantially minimal area including the connectivity cell. A second area is a substantially minimal area including at least a part of each of multiple portions of the integrated circuitry. The portions are connectable to respective ones of the terminals while having a placement flexibility relative to the terminals. This placement flexibility of the portions is substantially equal to a placement flexibility of the second area within the first area.

Abstract: Circuitry within a processor delays the launching of data onto an external bus by a factor that is proportional to the ratio of an internal processor clock speed to the system or external bus clock speed. This delay provides a delay in the launching of data to external bus devices so that these slower speed external bus devices have enough time to capture the data.

Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible field in each page table entry and this reference bit is utilized to indicate if an associated system memory location has been accessed for a read or write operation.

Abstract: A circular dispatch queue is used to implement an instruction queue, in a microprocessor, in order to reduce the delay associated with the critical timing path between an instruction cache memory and the instruction queue. In the circular dispatch queue, instructions are never moved from one stage to another. Instead, pointers are maintained that indicate the top and bottom instructions within the circular dispatch queue. This technique removes inputs from the multiplexor between the register stages in the circular dispatch queue and the instruction cache memory, thus reducing the critical delay.

Abstract: A method and system are provided for maintaining memory coherency. A first device stores information. A second device is coupled to the first device. The second device inputs at least a portion of the information and outputs an indication that the portion is not to be cached by the second device. Rather than initializing other devices to "know" in advance that a cache memory is absent from a given device, a control signal indicates the device's intent to not cache the requested portion of information in a cache memory.

Abstract: A method and system are provided for communicating between devices. A signal is output from a first device. In response to the signal, at least one action is initiated by a second device. An indication is output of whether the second device completed the action and of whether operation of the second device is independent of the first device reoutputting the signal.

Abstract: A method and system are provided for processing instruction threads. Execution is initiated by a processing system of a first set of instructions including a particular instruction. The particular instruction includes an indication of a second set of instructions. In response to execution of the particular instruction and to the processing system being of a first type, the processing system continues executing the first set while initiating execution of the second set. In response to execution of the particular instruction and to the processing system being of a second type, the processing system continues executing the first set without initiating execution of the second set.

Abstract: Atomic memory references require a data processing system to present the appearance of a coherent memory system, which may be achieved in most multiprocessor systems by means of normal memory coherency systems. Writes or attempted writes to memory must be monitored by a processor in order to correctly resolve hits against the reservation state. In a two level cache system the second level cache filters bus operations and forwards to the processor any bus traffic that may involve data stored within the first level cache. This may be accomplished by enforcing an "inclusion" property wherein all data entries within the first level cache are required to be maintained within higher level caches. A problem arises when a block within a first level cache which has had a reservation pending is cast out and the second level cache no longer forwards bus traffic to the associated processor, despite the continued pendency of the reservation.

Abstract: A method and device of executing a load multiple instruction in a superscaler microprocessor is provided. The method comprises the steps of dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. The method further includes the step of maintaining a table that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. The method concludes by executing an instruction that is dependent upon source operand data loaded by the load multiple instruction into a register of the plurality of registers indicated by the instruction as a source register, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register.

Abstract: A first inverter includes a first input coupled to a first input node. Also, the first inverter includes a first output coupled to an output node. Further, the first inverter includes a voltage node. A second inverter includes a second input coupled to a second input node. Moreover, the second inverter includes a second output coupled to the voltage node.

Abstract: A data cache array which includes a plurality of cache lines wherein each cache line includes a selected block of data, a parity field, a content addressable field containing at least a portion of an address for that block of information and a data status field for providing an indication of data validity within that cache line. An allocation control cell is associated with each cache line and a pseudo least recently utilized (PLRU) logic circuit is provided within the data cache array for each group of cache lines. The pseudo least recently utilized (PLRU) logic circuit is then utilized to select and set a particular allocation control cell within each group of cache lines in response to utilization of those cache lines.

Abstract: There is disclosed a central controller for simultaneously testing the embedded arrays in a processor. Test data vectors are serially shifted into a latch and stored into each location in the embedded arrays of the processor. The test data are then read out of the embedded arrays into a read latch and serially shifted into a multiple input shift register, where a polynomial division is performed on the test vector data. If all memory locations in the embedded array function properly, a remainder value will result that is equal to a unique signature remainder for the test vectors used.

Abstract: A method and circuitry are provided for latching information. The information is selectively transferred from a selected one of: a first node (DIN) to a second node (416); and a third node (SIN) to a fourth node (419a-b). The transferred information is selectively latched by coupling the second node (416) to the fourth node (419a-b) in response to a signal (308, 410).

Abstract: A processing system and method of operation are provided. First translation information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first translation information and a first portion of a first address. Second translation information is stored. A logic state of a second match line is selectively modified in response to a comparison between the second translation information and a second portion of the first address. The logic state of the second match line is selectively modified in response to the logic state of the first match line. A second address is selectively output in response to the logic state of the second match line.

Abstract: A processing system and method of operation are provided. At least one execution unit processes information of a register in response to an instruction specifying the register. Each of multiple control units selectively allocates a respective one of multiple buffers to store the information in response to the instruction.

Abstract: A fault tolerant processing system including a prediction RAM employs a Lock Step Compare routine. The method developed allows the processing system to recover from single event upsets. In initialization, the branch prediction RAM is set to a known value. An engineering balance is achieved by adding logic to detect a branch RAM error and incurring the delay of re-initializing the entire RAM only when a RAM error has been detected.

Abstract: A processing system and method of operation are provided. In response to multiple branch instructions, an instruction is processed prior to execution of the branch instructions. In response to execution of any of the branch instructions, the processing of the instruction is cancelled prior to completion of the executed branch instruction.