Abstract: A method and system within a processor are disclosed for executing selected instructions among a number of instructions stored within a memory, wherein the processor has a maximum of instructions that can dispatched for execution during each processor cycle. A subset of the instructions are fetched from the memory for execution. A determination is then made whether the set of instructions includes an unresolved branch instruction. In response to a determination that the set of instructions includes an unresolved branch instruction, a prediction is made whether a branch indicated by the branch instruction will be taken or will not be taken. In response to a prediction that the branch will be taken, a nonsequential target instruction indicated by the branch instruction is fetched from memory.

Abstract: A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved from memory. A selected instruction among the number of instructions is decoded to determine if the selected instruction would be noneffective if executed by the processor. In a preferred embodiment of the present invention, noneffective instructions include instructions with invalid opcodes and instructions that would not change the value of any data register within the processor. In response to determining that the selected instruction would be noneffective if executed by the processor, the selected instruction is recoded into a specified instruction format prior to dispatching the selected instruction to one of the number of execution units.

Abstract: A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic between the first and second buses. Using the logic, an action of a first bus device is enabled in response to a condition in which a second bus device waits for the action while the first bus device waits for a separate action on the second bus.

Abstract: A method for selectively executing speculative load instructions in a high-performance processor is disclosed. In accordance with the present disclosure, when a speculative load instruction for which the data is not stored in a data cache is encountered, a bit within an enable speculative load table which is associated with that particular speculative load instruction is read in order to determine a state of the bit. If the associated bit is in a first state, data for the speculative load instruction is requested from a system bus and further execution of the speculative load instruction is then suspended to wait for control signals from a branch processing unit. If the associated bit is in a second state, the execution of the speculative load instruction is immediately suspended to wait for control signals from the branch processing unit.

Abstract: A method and system in a data processing system for transferring data from a first device to a second device within the data processing system. The data processing system includes a data bus, an address bus, a first address space associated with a memory and a second address space associated with an input/output device. Initially, a transfer signal is transmitted in the data processing system. The transfer signal identifies the transfer as a transfer concerning an address in the second address space associated with the input/output device. A first address package is then transmitted to the second device from the first device on the address bus. The first address package includes a transfer identifier, a first identifier associated with the first device and a second identifier associated with the second device. A second address package, comprising a byte count and an address, are transmitted to the second device from the first device on the address bus.

Abstract: An apparatus for handling special cases outside of normal floating-point arithmetic functions is provided that is used in a floating-point unit used for calculating arithmetic functions. The floating-point unit generates an exponent portion and a mantissa portion and a writeback stage is coupled to the exponent portion and to the mantissa portion and is specifically used to handle the special cases outside the normal float arithmetic functions. A spill stage is also provided and is coupled to the writeback stage to receive a resultant exponent and mantissa. A register file unit is coupled to the writeback stage and the spill stage through a plurality of rename busses, which are used to carry results between the writeback stage and spill stage and the register file. The spill stage is serially coupled to the writeback stage so as to provide a smooth operation in the transition of operating on the results from the writeback stage for the exponent and mantissa.

Abstract: A fault-tolerant computer system having shadow registers for storing the contents of a primary array into a shadow array at the completion of a stored instruction execution. This is accomplished in one clock cycle with all registers being shadowed simultaneously. During rollback of execution steps for a checkpoint retry, the shadow register files provide a signal cycle unload of the shadow array into the primary array. LSSD latches are used in the shadow register file.

Abstract: A method and structure are provided for connecting to integrated circuitry. A connectivity cell includes multiple terminals formed within the integrated circuitry. The connectivity cell further includes at least one metal layer connected to at least one of the terminals. A first area is a substantially minimal area including the connectivity cell. A second area is a substantially minimal area including at least a part of each of multiple portions of the integrated circuitry. The portions are connectable to respective ones of the terminals while having a placement flexibility relative to the terminals. This placement flexibility of the portions is substantially equal to a placement flexibility of the second area within the first area.

Abstract: A processing system and method of operation are provided. Multiple instructions are dispatched in a sequence to execution circuitry. Ones of the instructions are executed with the execution circuitry, and respective results are output in response thereto, Each executed instruction is completed in response to finishing execution of each instruction preceding the executed instruction in the sequence, independent of whether the results are stored in at least one storage location specified by the completed instructions.

Abstract: A method and apparatus are provided for generating a phase-controlled clock signal within a microprocessor. A first clock signal having a first frequency is input. After a reset event, the first clock signal transitions in a first direction at a time t. A second clock signal is output having a second frequency related to the first frequency by a non-integer ratio. The second clock signal transitions in the same direction as the first clock signal at time t.

Abstract: A method and system are provided for self-timed processing. An operation is executed with a functional unit. A timing of the operation execution is simulated with a tracking element, and a tracking signal is output. A sequencing signal is varied to the functional unit in response to the tracking signal.

Abstract: A processing system and method of operation are provided. Multiple instructions are dispatched in a sequence to execution circuitry for execution. For each instruction, a determination is made in advance of execution about whether an exception is possible to result from execution of the instruction. An instruction is completed in response to determining an exception does not result from execution of the instruction and of each instruction preceding the instruction in the sequence, independent of whether the execution circuitry has finished execution of each instruction for which an exception is not possible.

Abstract: A processing system and method of operation are provided. A determination is made about whether to dispatch an instruction to execution circuitry for execution. After determining to dispatch the instruction, a determination is made about whether an exception condition exists for the instruction. The instruction is dispatched to the execution circuitry. In response to determining an exception condition exists for the instruction, an indication is output to inhibit execution of the instruction by the execution circuitry.

Abstract: A method and system are provided for prefetching information in a processing system. A first memory has multiple first locations. At least one of the first locations stores information including an address of a different first location, the different first location having been referenced in the first memory after a previous reference to the one first location. A second memory has at least one second location storing information from the one first location, including the address. Information is prefetched to the second memory from the address of the first memory, in response to a reference to the second location.

Abstract: A data processing system is provided. The system includes a window based display for displaying display windows. A processor executes multiple interleaved data processing tasks. The processor is able to trigger execution of a second task by the processor in response to execution of a first task by the processor The first and second tasks are associated with one or more of the display windows. The processor controls display of the associated display windows on the display. If the processor triggers execution of the second task in response to execution of the first task, the processor controls display of the second task's display window(s) to be visually connected to and move with the first task's display window(s) in response to data identifying the first task's display window(s).

Abstract: A processing system and method of operation are provided, In response to a branch instruction, a first instruction is processed so that a storage location is associated with the first instruction prior to execution of the branch instruction. In response to execution of the branch instruction, a second instruction is processed independent of information previously stored in the storage location so that the storage location is associated with the second instruction prior to completion of the branch instruction.

Abstract: Content addressable memory circuitry and a method of operation are provided. First information is stored. A logic state of a first match line is selectively modified in response to a comparison between the first information and second information. Also, third information is stored. A logic state of a second match line is selectively modified in response to a comparison between the third information and fourth information. A logic state of the second match line is selectively modified in response to the logic state of the first match line.

Abstract: A method and system for enhanced instruction dispatch efficiency in a superscalar processor system having a plurality of intermediate storage buffers, a plurality of general purpose registers, and a storage buffer index. Multiple scalar instructions may be simultaneously dispatched from a dispatch buffer to a plurality of execution units. Each of the multiple scalar instructions generally include at least one source operand and one destination operand. A particular one of the plurality of intermediate storage buffers is assigned to a destination operand within a selected one of the multiple scalar instructions. A relationship between the particular one of the plurality of intermediate storage buffers and a designated one of the plurality of general purpose registers is stored in the storage buffer index at that time when the instruction which has been dispatched is replaced in the dispatcher by another instruction in the application program sequence.

Abstract: A Carry-Save Adder circuit having differential signal response and output is provided. The circuit includes a pair of cross-coupled transistors powered by an upper voltage rail. The output of a first transistor of the pair of cross-coupled transistors is connected to the output of a first precharge transistor that is powered by the upper rail and controlled by a clock. The output of a second transistor of the pair of cross-coupled transistors is connected to the output of a second precharge transistor that is powered by the upper rail and controlled by the clock. A logic circuit is wired to perform a logical function, either a Sum or a Carry function, and has a plurality of inputs, an output, and a complementary output. The output of the logic circuit is connected to the output of the first transistor of the pair of cross-coupled transistors, and the complementary output is connected to the output of the second transistor of the pair of cross-coupled transistors.

Abstract: A computer memory system having partitioned page address for instructions and operands. The partitioning scheme for the virtual addressing memory minimizes the delay between the translation logic and the page translation RAMs. Computer processor performance is delayed by only a single clock cycle by the sharing of the memory address bus control between two address processors.