Patents Represented by Attorney, Agent or Law Firm Michael F. Heim
  • Patent number: 6564288
    Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to a control logic in a memory controller, that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles, or may throttle down the operating speed of the memory devices, or may place some or all of the memory devices in a low power mode until conditions improve. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: May 13, 2003
    Assignee: Hewlett-Packard Company
    Inventors: Sompong P. Olarig, John E. Jenne
  • Patent number: 6529984
    Abstract: A multiphase IEEE 1394 network of nodes requires all nodes to broadcast their current understanding of the phase of the bus (e.g., odd or even). Even if a node is not requesting ownership of the bus, it must send a message that indicates which phase that node believes to be the current phase of the network. If a node that does not need ownership of the bus believes the bus currently is in the odd phase, then that node will transmit a “None_odd” message indicating the node's understanding that the bus is in the odd phase. Similarly, if a node that does not need the bus believes the bus currently is in the even phase, then that node will transmit a “None_even” message indicating the node's understanding that the bus is in the even phase. Preferably, the current bus owner will not switch the phase of the bus until all nodes have a correct understanding of the current phase of the bus.
    Type: Grant
    Filed: March 29, 2000
    Date of Patent: March 4, 2003
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Michael D. Johas Teener, David R. Wooten
  • Patent number: 6529044
    Abstract: A conditional clock gate is implemented that equalizes load conditions on clocked transistor gates to provide a better quality clock signal in a clock distribution network. The conditional clock gate may be implemented as either a NAND gate or a NOR gate. According to one embodiment, a pre-charge transistor is that equals clock loading when the enable signal is de-asserted. The pre-charge transistor charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. In another embodiment, a pre-discharge transistor is implemented that charges a terminal of a clocked transistor during certain clock states to mimic load conditions that exist when the enable signal is asserted. Conditional clock gates may also be implemented with multiple enable inputs using these same prnciples.
    Type: Grant
    Filed: July 31, 2001
    Date of Patent: March 4, 2003
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: Daniel William Bailey
  • Patent number: 6498460
    Abstract: A power management scheme for a computer system prioritizes battery charging. The scheme includes determining when the output of a power adapter, which powers a computer and a battery subsystem, has reached or is about to reach a threshold which may be the power budget for the computer system. When this happens, rather than throttling battery charging, the system throttles back an aspect of the computer. Alternatively, after the computer has been throttled back, if the power budget still is being exceeded or is about to be exceeded again, then battery charging can be throttled back. In yet another embodiment, battery charging can be throttled first, followed, if necessary, by computer throttling.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: December 24, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: Lee W. Atkinson
  • Patent number: 6498716
    Abstract: The present invention is a power distribution assembly for distributing power about a rack mounted server system. In particular, each chassis of a rack mounted server system is provided power through a power distribution assembly that is hinged to a back of the rack of the server system. Each of the power distribution assemblies may be in either an open position or a closed position. In a closed position, each of the power distribution assemblies is rotated to lie very close to a backplane board of a chassis of the server system. In an open position, each of the power distribution assemblies is swung around so that full access may be had to the backplane boards of the chassis in the server system.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: December 24, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Everett R. Salinas, Allen T. Morrison
  • Patent number: 6496945
    Abstract: A computer system implementing a fault detection and isolation technique that tracks failed physical devices by identification (ID) codes embedded in each component of the computer for which the ability to detect faults and isolate failed devices is disclosed. The computer system comprises one or more CPU's, one or more memory modules, a master control device, such as an I2C master, and a North bridge logic device coupling together the CPU's, memory modules, and master control device. The master control device also connects to the CPU's and memory modules over a serial bus, such as an I2C bus. Each CPU and memory module includes an ID code that uniquely identifies and distinguishes that device from all other devices in the computer system. The computer also includes a non-volatile memory device coupled to the CPU for storing a failed device log which includes a list of ID codes corresponding to failed physical devices.
    Type: Grant
    Filed: June 4, 1998
    Date of Patent: December 17, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Darren J. Cepulis, Sid Young, Jr.
  • Patent number: 6493824
    Abstract: A secure system and method is provided for remotely waking a computer from a power down state. In one embodiment, a network interface card receives incoming data packets via a network connector. A control module is coupled to the network connector and is configured to search the incoming packets for a wake-up pattern. The control module also verifies that the packet's destination address matches the destination address of the network interface card. If the destination addresses match and a wake-up pattern is found, the control module decrypts an encrypted value from the incoming packet and compares the result to an expected value. A successful comparison causes the control module to assert a signal to wake up the host computer. Preferably, a standard public/private key pair encryption scheme is used, and the source of the data packet encrypts the expected value with a private key.
    Type: Grant
    Filed: February 19, 1999
    Date of Patent: December 10, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Manuel Novoa, Adrian Crisan
  • Patent number: 6493836
    Abstract: A computer system with high-speed memory devices includes error checking logic that monitors the number and/or frequency of memory errors. The number and/or frequency of soft memory errors is provided to control logic in a memory controller, which intelligently modifies the frequency of memory calibration cycles based on the detected memory errors. Thus, in response to an unacceptable number of memory errors, the memory controller may increase the frequency of calibration cycles. The memory controller may include error checking logic that monitors memory errors on multiple memory channels, if multiple memory channel are provided, to enable the memory controller to modify calibration frequency on a channel-by-channel basis.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: December 10, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Sompong P. Olarig, John E. Jenne
  • Patent number: 6484232
    Abstract: A computer system with high-speed memory devices includes one or more temperature sensors and/or environmental sensors that monitor environmental parameters that may affect the operation of the high-speed memory devices. The sensor values are provided to control logic in a memory controller that can intelligently modify the operation of the memory devices in response to changing environmental conditions. Thus, in response to deteriorating environmental conditions, the memory controller may increase the frequency of calibration cycles. The sensors may be provided on multiple channels, if the memory system is configured with multiple channels, or may be individually associated with memory devices. In addition, the memory controller also monitors the expected remaining life of the memory devices, and the number of errors occurring in the memory devices, and based on these parameters, may change the frequency of the calibration cycles.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: November 19, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Sompong P. Olarig, John E. Jenne
  • Patent number: 6484222
    Abstract: A system is disclosed for facilitating operation of a peripheral bus, such as a PCI bus, that operates at multiple clock speeds. The system includes an expansion slot controller that identifies the number of peripheral devices that have been installed in the expansion slots, and further determines whether these devices support high speed operation. The expansion slots transmit a signal indicating the presence of a peripheral device in the slot, and also transmit a signal indicating whether the device is operable at the higher clock frequency. Once the expansion slot controller determines this information, it decides whether operation at the higher frequency is supported by the peripheral devices and by the bus bridge. The expansion slot controller informs each peripheral device of what the operating frequency will be, and transmits a signal to the PCI bus bridge indicating if high frequency operation will be supported.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: November 19, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: David M. Olson, Ashley H. Gorakhpurwalla
  • Patent number: 6482046
    Abstract: The present invention is related to a cable coupling system for supplying DC power in rack-mounted server systems. The cable coupling system involves grouping related power supply and power return cables and placing ends of those cables in a cable-end housing. Electrically contacting the ends of the cables takes place through apertures in the back surface of the cable-end housing and corresponding electrical contact pins on a connection area of the rack-mounted system. The system also includes a connection guide having a lip that insures that the cable-end housing only connects to the electrical contact pins in one direction, thereby insuring that the polarity is not reversed in the supply of DC power. Further, the lip portion of the connection guide, in combination with a pry aperture on the top of the cable-end housing, assists removal of the cable-end housing by providing locations whereby a screw driver or other mechanism can be used to pry the cable-end housing.
    Type: Grant
    Filed: August 21, 2001
    Date of Patent: November 19, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: Everett R. Salinas
  • Patent number: 6476725
    Abstract: A media meter mounts to a surface of a removable storage media or other product, and provides a visual indication of one or more parameters of the storage media or other product. The media meter includes circuitry that detects status signals transmitted by rf transmissions or directly connected by wires between an auxiliary memory device mounted on the storage media or product, or receives status signals via rf transmissions directly from the auxiliary memory. As another alternative, the media meter may be integrated with the auxiliary memory to receive status signals directly from the auxiliary memory. The status signals indicate the capacity of the storage media, the number of read and/or write errors that have occurred during back-up and retrieval, the number of times the storage media has been loaded with data or other information, and other dynamically-varying parameters.
    Type: Grant
    Filed: November 30, 2000
    Date of Patent: November 5, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Jerry G. Aguren, Edward M. Flynn
  • Patent number: 6473334
    Abstract: A multi-ported SRAM memory cell includes a pair of inverters that holds the data bit. The state terminals of the memory cell connect via a separate read and write data path to the bit lines. The read bit lines connect to a pull-down transistor stack. The first transistor in the stack is gated by the word line, and the second transistor is gated by the state terminal of the memory cell. If the word line is asserted and the second transistor is turned on by the state of the memory cell, the bit line is connected to ground, thus pulling the bit line low. Conversely, if the second transmitter is not turned on, the bit line stays at a high voltage level. In a preferred embodiment, the memory cell is isolated from the pull-down transistor stack by an isolation buffer, such as an inverter, which inverts the voltage on the state terminal of the memory cell.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: October 29, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Daniel William Bailey, Stephen Felix, Stephen E. Liles
  • Patent number: 6470289
    Abstract: A computer system having thermal control logic that efficiently cools the computer system. In accordance with one embodiment of the invention, the thermal control logic couples to a CPU module and a fan. The CPU module includes a pair of temperature response elements. One temperature response element located near or on the CPU core logic or die on which the CPU is fabricated. The other temperature response element is located near or on an exterior surface of the CPU module. The thermal control logic monitors the temperature of recorded by each temperature response element and controls the speed of the fan and the frequency of the CPU core clock independently. Preferably, the thermal control logic adjusts the fan speed as a function of the temperature recorded by the temperature element adjacent an exterior surface of the CPU module. The thermal control logic also adjusts the frequency of the CPU clock signal as a function of the temperature recorded by the temperature response element adjacent the CPU core.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: October 22, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Mark W. Peters, Richard H. Hodge
  • Patent number: 6460947
    Abstract: A battery casing is adapted to fit into at least two different receiving bays of different sizes. The casing includes an adapter panel which is movable into at least two positions. Moving the adapter panel to the first position increases the effective width of the casing, and allows the battery to be inserted securely into a first receiving bay. Moving the adapter panel to the second position maintains the original width of the casing. This allows the battery casing to be inserted securely into a receiving bay, which has the same width as that of the original casing.
    Type: Grant
    Filed: March 30, 2000
    Date of Patent: October 8, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: Chow Kum Wah
  • Patent number: 6442067
    Abstract: A computer system has a ROM device containing two separately flashed areas. Each area contains a firmware image. From the factory, the two firmware images are identical. Each image also contains the executable code to flash an image area. The ROM also contains a “boot block” sector that makes decisions as to which of the firmware images is the “active” image and which is the “inactive” image. The active image is copied from the ROM to a RAM device and executed from RAM during normal system operation. The inactive image normally is not executed. The boot block sector also contains code that performs a checksum verification on the active image during initialization and, if the checksum fails, switches the active/inactive status of the two firmware images to make the previously inactive image the active image. With two firmware images, the system can recover from a power failure occurring while flashing the ROM because the other firmware image is still available.
    Type: Grant
    Filed: May 23, 2000
    Date of Patent: August 27, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Rohit Chawla, Scott W. Dalton
  • Patent number: 6370656
    Abstract: A computer system comprises a variety of components transmitting variable-rate heartbeats to a heartbeat monitor, each heartbeat indicating that the component is functioning properly. In addition, selected components serve as proxies by transmitting heartbeats to indicate that another component is functioning properly. In the preferred embodiment, one or more central processing units (CPUs) transmit heartbeats to indicate proper CPU functioning, while a bridge logic device and a network interface card (NIC) transmit heartbeats as proxies for a memory device and an external computer system, respectively. The heartbeat monitor is capable of determining initial heart rates for each component and is further capable of adaptively varying the heart rates thereafter. If the age of the heartbeat sender is relatively young, then a relatively slow heart rate is specified. Faster heart rates are specified for older components.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: April 9, 2002
    Assignee: Compaq Information Technologies, Group L. P.
    Inventors: Sompong P. Olarig, John E. Jenne
  • Patent number: 6363473
    Abstract: A computer system that simulates a memory stack in a non-general purpose register set in the computer's CPU. The computer system can use the simulated memory stack to store a return address before jumping to a subroutine or use the simulated stack to store a data value for subsequent retrieval and use. The non-general purpose register set may include memory type range registers (MTRRs). One of the MTRRs is designated as the stack pointer register and is used to store a pointer index value which identifies which of the other MTRR registers is associated with the top of the simulated memory stack. The computer system preferably includes a non-volatile memory, such as a ROM, which contains executable instructions for implementing the simulated memory stack. The instructions provide for incrementing and decrementing the pointer index value and writing to and reading from the MTRR registers identified by the pointer index as associated with the top of simulated stack.
    Type: Grant
    Filed: April 1, 1999
    Date of Patent: March 26, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventors: Robert J. Volentine, Rahul G. Patel
  • Patent number: 6356965
    Abstract: A computer system is provided with a dynamically reconfigurable boot order. In one embodiment, the computer comprises a user input device, a nonvolatile memory, a network interface, a boot trigger, and a CPU. The CPU is coupled to the user input device to detect a predetermined key press, coupled to the boot trigger to detect the assertion of a system reset signal, and coupled to the nonvolatile memory to retrieve a system BIOS in response to assertion of the system reset signal. The CPU executes the BIOS to initialize the computer system, and as part of the system initialization, the CPU determines a first target boot-up device. Preferably if the predetermined key has been pressed during the system initialization, the CPU alters the default boot order to select the network interface as the first target boot up device. The network interface is configurable to retrieve an operating system from a network device for the CPU to execute.
    Type: Grant
    Filed: September 8, 1998
    Date of Patent: March 12, 2002
    Assignee: Compaq Computer Corporation
    Inventors: Paul J. Broyles, Don R. James, Jr.
  • Patent number: 6349035
    Abstract: A heat dissipating apparatus for use on a heat generating electric component inside a computer comprises an interposer mounted on the heat generating electric component and a heat absorbing member including a heat absorber, a bracing member, and a spring biasing said heat absorber toward the bracing member. The heat absorbing member is moveable between a first position in which the interposer is compressed between the heat absorber and the bracing member and a second position in which the interposer is not compressed between the heat absorber and the bracing member.
    Type: Grant
    Filed: September 29, 2000
    Date of Patent: February 19, 2002
    Assignee: Compaq Information Technologies Group, L.P.
    Inventor: David J. Koenen