Abstract: A portable notebook computer having a thickness of only one inch is obtained by provision of a computer housing containing a keyboard assembly and a motherboard positioned directly below the keyboard assembly, the keyboard assembly and the motherboard thereby defining a region in the enclosure. The other components comprising the computer; i.e. a hard disk drive, a PCMCIA option slot, a trackball assembly, and a DC to DC convertor, are positioned in an adjacent and generally co-planar relationship with this region. A battery housing is mounted externally on the computer housing for supplying electrical power to the computer.

Abstract: A structure and related method for generating phase enable signals for a multi-phase switching power supply with the characteristic that each signal has the same frequency, but each differs in phase relationship. The structure includes a clock circuit coupled to a shift register and clocking the shift register. The shift register has one of its outputs coupled to its shift input signal line. Clocking of the shift register with the clock circuit produces a series of phase enable signals, at the shift register's shift output signal lines, to be coupled to switching phases of a multi-phase switching power supply. The circuit easily adapts to varying number of phases of the multi-phase switching power supply by changing which of the several shift output signals couples back to the shift input signal.

Abstract: A computer system is provided with a dynamically reconfigurable boot order. In one embodiment, the computer comprises a network interface, a nonvolatile memory, and a CPU. The network interface may be coupled to a network to receive a “wake-up” data packet, that is, a data packet that includes a predetermined data pattern for which the network interface can be configured to scan. Upon detecting the wake-up data packet, the network interface can initiate a computer boot-up sequence. The CPU begins a boot-up sequence by retrieving a BIOS from the nonvolatile memory. One portion of the boot-up sequence specified by the BIOS includes determining and accessing a series of target boot devices to locate and retrieve an operating system. Preferably, the order of the series of target boot devices (i.e. the “boot order”) is different from a default boot order if the network interface initiated the current boot-up sequence. Otherwise, the default boot order is used.

Abstract: A computer system includes an adaptive memory arbiter for prioritizing memory access requests, including a self-adjusting, programmable request-priority ranking system. The memory arbiter adapts during every arbitration cycle, reducing the priority of any request which wins memory arbitration. Thus, a memory request initially holding a low priority ranking may gradually advance in priority until that request wins memory arbitration. Such a scheme prevents lower-priority devices from becoming “memory-starved.” Because some types of memory requests (such as refresh requests and memory reads) inherently require faster memory access than other requests (such as memory writes), the adaptive memory arbiter additionally integrates a nonadjustable priority structure into the adaptive ranking system which guarantees faster service to the most urgent requests.

Abstract: A computer system includes a CPU and a memory device coupled by a bridge logic unit. CPU to memory write requests (including the data to be written) are temporarily stored in a queue in the bridge logic unit. The bridge logic unit preferably begins a write cycle to the memory device before all of the write data has been stored in the queue and available to the memory device. By beginning the memory cycle as early as possible, the total amount of time required to store all of the write data in the queue and then de-queue the data from the queue is reduced. Consequently, many CPU to memory write transactions are performed more efficiently and generally with less latency than previously possible.

Abstract: The present invention provides an optical device for the measurement of flow rates of fluid through a pipe. The device broadly comprises a narrow frequency light source, an optical delivery system, a collector for light scattered from particles in the fluid, and a photo detector. In a preferred embodiment, the optical delivery system and the collector are contained within the pipe.

Abstract: A computer system is provided with a non-volatile memory module that is shared by a plurality of system components during system initialization. In one embodiment, the computer system comprises a processor for executing program instructions, a memory device for storing data and program instructions, a number of integrated system components for carrying out specialized functions, a bridge logic device for communication between the processor, memory, and system components, and a shared non-volatile memory module for storing configuration information for each of the system components. Each of the integrated system components is configured to retrieve its associated configuration information from the shared non-volatile memory module during initialization, rather than from a dedicated non-volatile memory as is conventionally done. This consolidation of multiple non-volatile memories into a single memory module provides numerous advantages including reduction of cost and required space on the motherboard.

Abstract: A computer system includes a processor, a memory device, at least one expansion bus, and a bridge device coupling the processor, memory device, and expansion bus together. The bridge device preferably includes a memory controller that is capable of arbitrating among pending memory requests, and in certain situations, completing the current cycle after the next cycle begins. This allows executing at least two memory requests concurrently, thus improving bus utilization and retrieving and storing data in memory occurs more efficiently. The memory controller can complete the current memory cycle during the next cycle when the next memory request to be executed will result in a bank miss and a least recently used tracker is currently tracking its maximum number of open memory pages and banks.

Abstract: A computer system is provided with a multifunction power switch. In addition to the normal function of turning the computer on and off, the power switch has the additional function of clearing CMOS memory. In one embodiment, pressing the power switch while the computer is connected to a power source turns the computer on and off, and when the computer is disconnected from the power source, the CMOS memory may be cleared by pressing and holding the power switch for a predetermined time delay, e.g. 10 seconds. As a precaution against malicious clearing of CMOS memory, activation of this feature may be disabled as long as the computer cover is closed. In this case, the computer cover would have to be at least partially removed before the power button is pressed and held to clear CMOS. An LED may be provided which illuminates to indicate the success of the CMOS clearing operation.

Abstract: A computer system that includes a CPU, a memory and a memory controller for controlling access to the memory. The memory controller generally includes arbitration logic for deciding which memory request among one or more pending requests should win arbitration. When a request wins arbitration, the arbitration logic asserts a “won” signal corresponding to that memory request. The memory controller also includes synchronizing logic to synchronize memory requests, corresponding to a first group of requests, that win arbitration to a clock signal and an arbitration enable signal. The synchronizing logic includes an AND gate and a latch for synchronizing the won signals. The memory controller also asynchronously arbitrates a second group of memory requests by asserting a won signal associated with the second group requests that is not synchronized to the clock signal.

Abstract: A computer system includes a CPU, a memory device, two expansion buses, and a bridge logic unit coupling together the CPU, the memory device and the expansion buses. The CPU couples to the bridge logic unit via a CPU bus and the memory device couples to the bridge logic unit via a memory bus. The bridge logic unit generally routes bus cycle requests from one of the four buses to another of the buses while concurrently routing bus cycle requests to another pair of buses. The bridge logic unit preferably includes four interfaces, one each to the CPU, memory device and the two expansion buses. Each pair of interfaces are coupled by at least one queue; write requests are stored (or “posted”) in write queues and read data are stored in read queues.

Abstract: A computer system includes a CPU and a memory device coupled by a North bridge logic unit to an expansion bus, such as a PCI bus. A South bridge logic connects to the expansion bus and couples various secondary busses and peripheral devices to the expansion bus. The South bridge logic includes internal control devices or master devices that are designed to run master cycles on the expansion bus. The master devices couple to the expansion bus through a common expansion master interface, which executes master cycles on the expansion bus on behalf of the master devices. The South bridge also includes an internal modular master expansion bus coupling the internal master devices to the common master interface. The internal modular master expansion bus permits the master devices to run master cycles to any expansion bus by understanding a standardized group of signals represented by the internal modular master expansion (IMAX) bus.

Abstract: A computer system includes a South bridge logic that connects an expansion bus to one or more secondary expansion busses and peripheral devices. The South bridge logic includes internal control devices that are targets for masters on the expansion bus. The target devices couple to the expansion bus through a common expansion target interface, which monitors and translates master cycles on the expansion bus on behalf of the target devices. The South bridge includes an ACPI/power management logic capable of supporting a Device Idle mode in which selected I/O device may be placed in a low power state. To prevent cycles from being run to a device in a low power state, the ACPI/power management includes status registers that are used to determine when a device in low power mode is the target of an expansion bus cycle. If such a cycle occurs, the cycle is intercepted and an SMI signal is transmitted to the CPU. In addition, the target interface responds to the master by asserting a retry signal.

Abstract: A method and apparatus is disclosed for use in an implantable device that communicates with an external device through pulse position modulation. A timing generator is provided as part of the implantable device that determines the phase uncertainty between an external signal and an internal cock signal. The phase uncertainty then is added to the preset delay period to more precisely control the position of the response. The phase uncertainty is measured by a dual slope circuit that varies a state variable (which can be a digital timer, a capacitor voltage, or the like) at a fixed rate with either a positive or negative slope. When the external signal is detected, the stat variable is reset and then decreased at a fixed rate until the next positive edge of the clock signal. The state variable then is increased at the same rate until the subsequent positive clock edge. The resulting variable value is proportional to the phase uncertainty.

Abstract: A poppet and orifice mud pulser assembly is disclosed for use in an MWD system. The mud pulser is capable of generating pressure pulses in the column of drilling mud of various amplitudes to increase the data rate of the mud pulse telemetry system. The mud pulser includes a piston assembly that positions the poppet with respect to the orifice. The piston assembly comprises part of a by-pass conduit which defines a mud flow path around the orifice. Mud flow in the piston assembly generates a force tending to shut the poppet, because the surface area of the piston A.sub.2 is greater than the surface area of the poppet A.sub.1. Mud flow through the conduit (and thus through the piston) tends to force the poppet into a closed position because the force on the piston is greater than the force on the poppet, because of the greater surface area of the piston. A pilot valve is provided to enable and disable flow through the conduit, thus allowing the poppet to open and close.

Abstract: A speech categorization system includes first and second timers which generate first and second measured durations indicative of duration of selected higher and lower amplitude segments included in a voice message. A higher amplitude segment is classified in a first category when the first and second measured durations corresponding to the higher amplitude segment and an adjacent lower amplitude segment satisfy a classification test, and a counter counts the number of the higher amplitude segments classified in the first category. Accented syllables in the higher amplitude segment are recognized to aid classification.

Abstract: A method and apparatus is disclosed for an analog-to-digital converter (ADC) to minimize power consumption. The ADC of the present invention minimizes the number of clock cycles required to determine the correct digital code for a particular sample point on an electrogram signal, thus making it possible to turn off some or all of the ADC logic during idle periods. The ADC includes prediction logic that provides a starting point for subsequent digital code representations of the electrogram signal. The prediction logic receives recent code conversions values to predict a current digital code value. This predicted digital code is converted to an analog value and compared with the actual electrogram signal. Next, the ADC adds (or subtracts) a constant value (C) to (or from) the predicted code and compares the result to the electrogram signal.

Abstract: An artificial neuron for use in a neural processing network comprises a plurality of input signal lines, an arrangement for computing a nonlinear function of the sum of the inputs multiplied by associated weights, and a saturating delta-sigma modulator which oversamples the computed value and produces an encoded neuron output signal. Conversion of signals for use by these neurons preferably is performed by delta-sigma modulators at the inputs to the neurons, which may be incorporated directly into sensors. Processing of the output signals from the neuron includes low-pass filtering and decimation. The present invention may be used in many diverse areas. For example, arrays of sensors with delta signal modulators may be coupled with a network of the neurons to form an intelligent vision system. Linear signal processing, both conventional and adaptive, can be done by a simple neuronal system that operates linearly.

Abstract: A method and apparatus is disclosed for use in an implantable device that communicates with an external device through pulse position modulation. A timing generator is provided as part of said implantable device that determines the phase uncertainty between an external signal and an internal cock signal. The phase uncertainty then is added to the preset delay period to more precisely control the position of the response. The phase uncertainty is measured by a dual slope circuit that varies a state variable (which can be a digital timer, a capacitor voltage, or the like) at a fixed rate with either a positive or negative slope. When the external signal is detected, the state variable is reset and then decreased at a fixed rate until the next positive edge of the clock signal. The state variable then is increased at the same rate until the subsequent positive clock edge. The resulting variable value is proportional to the phase uncertainty.

Abstract: An automatic cementing system and method are disclosed for precisely controlling the density of a slurry during a continuously mixed cement application. The system includes an input water line and a dry cement hopper for supplying water and dry cement, respectively, to a mixing chamber. The mixing chamber includes two chambers, Chamber A and Chamber B, for thoroughly mixing the water and cement together to form a cement slurry. Chamber B includes a level sensor for measuring the change in slurry level. The input line includes a pump for supplying the water to the mixing chamber, and a flow meter for measuring the rate at which the water is supplied. Similarly, the hopper includes a rotary valve for regulating the rate at which the dry cement is supplied to the mixing chamber and a speed sensor for measuring the speed of the rotary valve. A discharge line with a discharge pump and a discharge flow meter receives and discharges cement slurry.