Abstract: An Analog-to-Digital Converter (ADC) is provided. An embodiment of the ADC includes a modified Delta modulator including a digital feedback loop, and a digital Sigma-Delta modulator configured within the feedback loop. Embodiments of the invention provide analog functionality with all the benefits of a digital design process as well as various other advantages provided by a Delta-Sigma-Delta modulator configuration.

Abstract: A method is disclosed for making a non-volatile memory cell on a semiconductor substrate. A select gate structure is formed over the substrate. The control gate structure has a sidewall. An epitaxial layer is formed on the substrate in a region adjacent to the sidewall. A charge storage layer is formed over the epitaxial layer. A control gate is formed over the charge storage layer. This allows for in-situ doping of the epitaxial layer under the select gate without requiring counterdoping. It is beneficial to avoid counterdoping because counterdoping reduces charge mobility and increases the difficulty in controlling threshold voltage. Additionally there may be formed a recess in the substrate and the epitaxial layer is formed in the recess, and a halo implant can be performed, prior to forming the epitaxial layer, through the recess into the substrate in the area under the select gate.

Abstract: A TMOS device (10) is formed using a semiconductor layer (16) of a first type. First and second regions (62,64) of the second type are formed in the semiconductor layer and are spaced apart. A third region (68) is formed in the semiconductor layer by implanting. The third region is between and contacts the first and second doped regions, is of the second conductivity type, and is less heavily doped than the first and second doped regions. A gate stack (67) is formed over a portion of the first doped region, a portion of the second doped region, and the third doped region. By implanting after forming the gate stack, fourth and fifth regions (98,100) of the first type are formed in interior portions of the first and second doped regions, respectively. The third region being of the same conductivity type as the first and second regions reduces Miller capacitance.

Abstract: A three-axis MEMS transducer featuring a caddie-corner proof mass comprises a planar main body portion of conductive material and a planar extra mass caddie-corner feature. The main body portion includes a width, length, and at least four side edges. An x-axis sense direction is defined from a first side edge to an opposite first side edge and a y-axis sense direction is defined from a second side edge to an opposite second side edge. The x-axis sense direction is perpendicular to the y-axis sense direction. The main body portion further includes at least two corners. The caddie-corner feature is positioned about at least one of the two corners of the main body portion. The caddie-corner feature and the main body portion comprise a single proof mass having a z-sense pivot axis disposed at an angle of ninety degrees to a diagonal extending from the caddie-corner feature to an opposite corner of the main body portion.

Abstract: A method for damage avoidance in transferring a monocrystalline, thin layer from a first substrate onto a second substrate involves epitaxial growth of a sandwich structure with a strained epitaxial layer buried below a monocrystalline thin layer, and lift-off and transfer of the monocrystalline thin layer with the cleaving controlled to happen within the buried strained layer in conjunction with the introduction of hydrogen.

Abstract: A NICAM processing method includes receiving and temporarily storing a current frame of A-channel and B-channel input data into a first memory at a first clock rate. Companded A-channel and B-channel data of a previous frame are read from a second memory at a second clock rate and in a manner for interleaving the previous frame companded A-channel and B-channel data into the NICAM standard required interleaved format, wherein the companded A-channel and B-channel data of the previous frame was temporarily stored during a previous frame into the second memory in a format other than an interleaved format according to NICAM standard requirements.

Abstract: An ESD protection circuit (20) includes an ESD device (24) and an isolation diode element (30). The ESD device includes a drain-source junction isolated ESD transistor (26,28). The isolation diode element is coupled in series with the ESD device and configured for providing ESD protection to a transistor device (22) needing ESD protection. Responsive to ?Vgs conditions on a gate of the protected transistor device, the series coupled isolation diode element prevents a forward biasing of the drain-source junction of the ESD transistor prior to a breakdown condition of the isolation diode element. In addition, responsive to an ESD event sufficient to cause damage to the protected transistor device, the series coupled isolation diode element permits an occurrence of the breakdown condition. Furthermore, the ESD protection circuit can operate in both (i) a polarity of normal operation of the protected device and (ii) an opposite polarity other than in normal operation of the protected device.

Abstract: An integrated MIS capacitor structure has a bottom electrode, a capacitor dielectric overlying the bottom electrode, and a plurality of capacitor top plates overlying the capacitor dielectric. In one form each capacitor top plate has a principal dimension and a lesser dimension, wherein individual capacitor top plates of the plurality are arranged proximate and adjacent to one another in an array along respective principal dimensions thereof. The bottom electrode is shared among the plurality of capacitor top plates. At least one of a plurality of conductive stripes is positioned on opposite sides of each capacitor top plate along the principal dimension of a respective capacitor top plate. The structure also has a grounded top metal layer and an inter-level dielectric. An external ground via is disposed adjacent at least one side edge of the plurality of capacitor top plates.

Abstract: A method of generating and placing of test structures in test chips comprises creating a control data set for one or more device types, generating a test structure layout in response to the control data set, and placing the test structure layout within a given pad array layout of the at least one pad array as a function of a set of keywords. The control data set includes (i) a set of keywords and (ii) parameter geometries for corresponding ones of test structures associated with the set of keywords. The keywords each define at least (a) one or more pad allocations for each test structure of a given device type, (b) a number quantity of test structures for the given device type, and (c) placement information of the test structures relative to one or more pad allocations of at least one pad array. The pad array layout is configured for enabling a fabrication of corresponding test structures in test chips.

Abstract: A method for dynamically determining frames required to build a complete picture in an MPEG video stream includes decoding an order of frames in the MPEG video stream according to a dependency vector model. The dependency vector model is configured for determining a dependency vector as a function of the decode order video stream for seamless operation over several types of MPEG streams. The method also includes performing frame accurate representations of the MPEG stream in a bidirectional fashion as a function of the dependency vector determined according to the dependency vector model.

Abstract: An integrated shunt capacitor comprises a bottom plate (86,88), a capacitor dielectric (92) overlying a portion of the bottom plate, a top plate (62) overlying the capacitor dielectric, a shield (74) overlying a portion of the top plate (62); and a metallization feature (70) disposed about and isolated from at least two sides of the top plate (62), the metallization feature (70) for coupling the bottom plate (86,88) to the shield (74). In one embodiment, an RF power transistor has an impedance matching network including an integrated shunt capacitor as described herein.

Abstract: A method for implementing a Media Independent Handover (MIH) service between one or more of a heterogeneous and a non-heterogeneous network comprises providing an MIH beacon from one or more of a network (Net) or a mobile node (MN); acknowledging a receipt of the MIH beacon by another of the network (Net) or the mobile node; and facilitating handover (HO) services in response to an acknowledged receipt, and further in response to an MIH beacon message subsequently provided from one or more of the network (Net) or the mobile node. In one embodiment, the MIH beacon comprises at least an MIH-Capability (MIHC) flag, the MIHC flag having one of a first state or a second state.

Abstract: A method for performing failure analysis on a semiconductor device under inspection includes preparing of a device sample using an encapsulation material containing a dye, the prepared device sample possibly including a failure area having wicked in encapsulation material containing the dye. The prepared device sample is then sectioned to facilitate viewing a cross section face of the device under inspection. Lastly, a dark field analysis on the prepared device sample is performed with the use of dark field illumination. Responsive to at least one failure area containing wicked in encapsulation material with dye occurring on the cross section face of the device under inspection, the failure area can be readily identified as well as a contrast and perspective of remaining portions of the cross section face being maintained.

Abstract: A method of forming a dielectric layer structure on a supporting semiconductor structure having a first surface comprises providing a first beam of oxide; depositing a first layer of oxide on the first surface of the supporting semiconductor structure using the first beam of oxide, wherein the first layer of oxide has a second surface; terminating the first beam of oxide, and concurrently providing a second beam of oxide, a beam of metal and a beam of oxygen, wherein the first and second beams of oxide are separate and distinct beams of oxide; and depositing a second layer of oxide on the second surface simultaneously using the second beam of oxide, the beam of metal, and the beam of oxygen.

Abstract: An integrated circuit comprises a processor configured for fetching and executing opcodes, a system bus, and a memory coupled to the processor via the system bus. The memory includes logic circuitry for detecting functional states of the memory, wherein the memory (a) supplies one or more programmed opcodes in response to detection of first functional states of the memory, and (b) supplies a hard coded opcode in response to detection of second functional states of the memory. The second functional states of the memory can include one or more of erase, write, self-test, and check-sum. The first functional states of the memory can include a functional state other than a second functional state.

Abstract: Methods and apparatus are provided for reducing substrate leakage current of RESURF LDMOSFET devices.

Abstract: A III-V based, implant free MOS heterostructure field-effect transistor device comprises a gate insulator layer overlying a compound semiconductor substrate; ohmic contacts coupled to the compound semiconductor substrate proximate opposite sides of an active device region defined within the compound semiconductor substrate; and a gate metal contact electrode formed on the gate insulator layer in a region between the ohmic contacts. The ohmic contacts have portions thereof that overlap with portions of the gate insulator layer within the active device region. The overlapping portions ensure avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer.

Abstract: A method of forming a compound semiconductor device comprises forming a gate insulator layer overlying a compound semiconductor substrate, defining an active device region within the compound semiconductor substrate, forming ohmic contacts to the compound semiconductor substrate proximate opposite sides of the active device region, and forming a gate metal contact electrode on the gate insulator layer in a region between the ohmic contacts. The ohmic contacts having portions thereof that overlap with portions of the gate insulator layer within the active device region. The overlapping portions ensure an avoidance of an undesirable gap formation between an edge of the ohmic contact and a corresponding edge of the gate insulator layer.

Abstract: A BTSC encoder includes dual channel ADC, sync separator, audio processor, filtering device, and a composite audio signal generating device. The filtering device includes a first filter for providing a filtered L+R signal, and a second filter for providing at least one of: i) a filtered and combined pilot and modulated L?R signal and ii) separately filtered pilot and modulated L?R signals. The composite audio signal generating device is responsive to the filtered L+R signal, and at least one of i) the filtered and combined pilot and modulated L?R signal and ii) the separately filtered pilot and modulated L?R signals for generating and outputting a composite analog audio signal. In all embodiments, the modulated L?R signal is filtered via an anti-splatter filter.

Abstract: A method of having transistors formed in enhanced performance crystal orientations begins with a wafer having a semiconductor substrate (12,52) of a first surface orientation, a thin etch stop layer (14,54) on the semiconductor substrate, a buried oxide layer (16,56) on the thin etch stop layer, and a semiconductor layer (18,58) of a second surface orientation on the buried oxide layer. An etch penetrates to the thin etch stop layer. Another etch, which is chosen to minimize the damage to the underlying semiconductor substrate, exposes a portion of the semiconductor substrate. An epitaxial semiconductor (28,66) is then grown from the exposed portion of the semiconductor substrate to form a semiconductor region having the first surface orientation and having few, if any, defects. The epitaxially grown semiconductor region is then used for enhancing one type of transistor while the semiconductor layer of the second surface orientation is used for enhancing a different type of transistor.