Abstract: A capacitor having a high dielectric constant and method of making the same is disclosed. The capacitor comprises a bottom electrode comprising a conductive oxide deposited upon a substrate by chemical vapor deposition. A dielectric layer having a high dielectric constant is deposited upon the conductive oxide. Lastly, a counter electrode is formed upon the dielectric layer.

Abstract: An ultrasonic jet semiconductor wafer cleaning apparatus for removing debris from a surface of a semiconductor wafer as the wafer is rotated about a prescribed axis in a cleaning plane is disclosed. The apparatus comprises a housing having a principal axis, an inlet port, and an outlet port; a means for producing focused ultrasonic waves of acoustic energy concentric with and incident the outlet port to form a jet stream of cleaning liquid released through the outlet port; a focal point positioning means for adjustably positioning a focal point of the focused ultrasonic wave producing means between a first focal point position and a second focal point position along an axis; and a means coupled to the housing for sweeping the housing in an reciprocating manner along a sweep path.

Abstract: A test probe assembly is disclosed having bucking beam displacement test probe units which are easily replaceable. Each test probe unit includes a wire and a slotted tube containing the wire,one end of the wire being attached to one end of the tube and the other end of the wire protruding from the other end of the tube. The wire slidably engages an inner diameter of the tube. Each tube is slotted at a plurality of locations along the longitudinal axis thereof to provide spaces for the buckling beam displacement of the respective wire when the protruding end of the wire is brought to bear against a device point to be tested. The slots are staggered so that adjacent ones are disposed radially opposite to each other with some overlap along the longitudinal axis of the tube. The test probe units are inserted in predetermined respective holes of an apertured block of insulating material in accordance with a pattern of device points to be tested.

Abstract: Contamination levels in plasma processes are reduced during plasma processing, by prevention of formation of particles, by preventing entry of particles externally introduced or by removing particles spontaneously formed from chemical and/or mechanical sources. Some techniques for prevention of formation of particles include interruption of the plasma by pulsing the source of plasma energy periodically, or application of energy to provide mechanical agitation such as mechanical shockwaves, acoustic stress, ultrasonic stress, vibrational stress, thermal stress, and pressure stress. Following a period of applied stress, a tool is pumped out (if a plasma is used, the glow is first discontinued), vented, opened and flaked or particulate material is cleaned from the lower electrode and other surfaces. A burst of filtered air or nitrogen, or a vacuum cleaner is used for removal of deposition debris while the vented tool is open.

Abstract: A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic thermal expansion coefficient. The second wafer comprises a second substrate having an insulation layer formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer.

Abstract: A method of fabricating a micro-coaxial wiring structure comprises forming a first insulation layer and patterning a trench therein. A first conductive layer is formed on the first insulation layer and having a shape conforming to the insulation layer and lining the trench. A second insulation layer is formed on the first conductive layer within the trench and having a shape conforming to the first conductive layer lining the trench. A conductive signal line having a predetermined aspect ratio for providing a desired value of resistance per unit length is formed on the second insulation layer within the trench. A third insulation layer is then formed. Lastly, a conductive shielding line is formed upon the third insulation layer, the conductive shielding line being aligned with the conductive signal line.

Abstract: A contactless method and apparatus for real-time in-situ monitoring of a chemical etching process for the etching of at least one wafer in a wet chemical etchant bath are disclosed. The method comprises the steps of providing at least two conductive electrodes in the wet chemical bath, said at least two electrodes being proximate to but not in contact with the at least one wafer; and monitoring an electrical characteristic between the at least two electrodes, wherein a prescribed change in the electrical characteristic is indicative of a prescribed condition of the etching process. Such a method and apparatus are particularly useful in a wet chemical etch station.

Abstract: An in-situ thickness monitoring/endpoint detection method and apparatus for chemical-mechanical polishing (CMP) of a dielectric layer on a top surface of a semiconductor wafer is disclosed. The apparatus comprises center and guard electrodes and associated electronic circuitry, including a high frequency, low voltage signal generating means, for converting a current which is inversely proportional to the dielectric layer thickness into a corresponding analog voltage. A position detection device triggers an analog-to-digital converter to convert the analog voltage into a digital signal while the wafer is located within a detection region as the wafer is being polished. A control means gathers the digital signals corresponding to the thickness data for processing and CMP device control.

Abstract: A method of thinning SOI films for providing ultra-thin active device regions having excellent thickness uniformity and further having self-aligned isolation regions between the active device regions is disclosed. A substrate having an isolation layer formed thereon and further having a single crystal silicon layer formed upon the isolation layer is first provided. A thermal oxide layer is grown upon the silicon layer, patterned in desired regions corresponding to polish stop regions positioned between predetermined active device regions, and etched. The silicon layer is thereafter etched according to the patterned thermal oxide layer with a high selectivity etch, thereby creating grooves in the silicon layer.

Abstract: A heat dissipation apparatus for dissipation of thermal energy from an isolated active silicon region to an underlying supportive substrate is disclosed. Such an apparatus comprises a diamond filled trench having walls extending through the isolated active silicon region, an underlying insulative layer, and into the supportive substrate, whereby said diamond filled trench provides a high thermal conductive path from said active silicon region to said substrate.

Abstract: A method for transferring a pattern through a photoresist layer in the fabrication of submicron semiconductor devices structures is disclosed. A photoresist is provided on a substrate and the same is imagewise exposed with a desired pattern to form exposed and unexposed patterned areas in the top surface of the photoresist. The photoresist is then baked to form cross-linked regions in the exposed pattern areas of the photoresist. Silylation is then performed to incorporate silicon into the unexposed patterned areas of the photoresist, wherein some incorporation of silicon occurs in the exposed patterned crosslinked areas of the photoresist. The patterned photoresist is subsequently etched using a high density, low pressure, anisotropic O.sub.2 plasma alone to produce residue-free images with vertical wall profiles in the photoresist. This method is particularly advantageous with RFI reactive ion etch systems.

Abstract: A method of forming a thin semiconductor layer having ultra-high thickness uniformity and upon which semiconductor structures can subsequently be formed is disclosed. The method comprises providing a primary substrate having a prescribed total thickness variation (TTV). A stack is formed upon the primary substrate for compressing thickness variation to be transferred into the thin semiconductor layer. An epitaxial silicon layer of a desired SOI thickness is formed upon the stack. The epitaxial silicon layer is then bonded to a mechanical substrate to form a bonded substrate pair, the mechanical substrate having a prescribed TTV and the bonded substrate pair having a combined TTV equal to the sum of the TTVs of the primary and mechanical substrates, respectively. The primary substrate is subsequently removed, wherein the combined TTV of the bonded substrate pair is transferred and compressed into the stack by a first compression amount.

Abstract: A method and the resulting product for isolating lightly doped silicon islands from each other and from a common substrate. The substrate is covered with a first heavily doped epi layer. The first layer is covered with a lightly doped second epi layer. A pair of spaced deep trenches are provided which extend from the top surface of the second layer, through the first layer and into the substrate. The interior walls of the trenches are lined with oxide. A pair of heavily doped reach-through diffusions extending from said top surface to the first layer is oriented perpendicularly to the deep trenches and fully extends between the trenches. The heavily doped reach-through diffusions and the contiguous first layer are removed by a single anisotropic etching step to yield silicon islands isolated by air except where the islands contact the oxide-lined deep trenches. The air isolation preferably is partially replaced with other dielectric material.

Abstract: A dry processing apparatus for plasma etching or deposition includes a chamber for plasma processing having an external wall for housing a work piece with a surface to be plasma processed. A source of an induction field is located outside the chamber on its opposite side from the work piece. A radio frequency induction field applied to the chamber generates a plasma. The plasma is confined within the external wall in the chamber by magnetic dipoles providing a surface magnetic field for confining the plasma. The surface magnetic field is confined to the space adjacent to the external wall. An R.F. generator provides an R.F. generated bias to the work piece. The chamber is lined with a material inert to a plasma or noncontaminating to the work piece, and the induction source in the form of a spiral or involute shaped induction coil is located on the exterior of the liner material on the opposite side of the chamber from the work piece.

Abstract: A method of making an improved bipolar transistor and the transistor itself having a double-self-aligned device structure are disclosed. The method and the transistor device provide self-alignment of collector-base and base-emitter junctions to each other, in addition to self-alignment of the base and emitter.

Abstract: A method of depositing Ge on a Si substrate in a reaction chamber includes the steps of: precleaning the substrate; evacuating the chamber to a pressure below 10.sup.-7 Torr; heating the substrate to 300.degree.-600.degree. C.; and providing a GeH.sub.4 /B.sub.2 H.sub.6 /He mixture of gas with a GeH.sub.4 partial pressure of 2-50 mTorr and a B.sub.2 H.sub.6 partial pressure of 0.08 to 2 mTorr.

Abstract: A semiconductor laser diode comprises a waveguide formed by an active layer sandwiched in between upper and lower cladding layers, wherein the cladding layers comprise a material having a bandgap that differs from that of the active layer. The waveguide is deposited on a structured substrate having a surface pattern that causes the waveguide to be bent near its ends, i.e., near cleaved or etched facets of the completed laser device thereby providing a non-absorbing mirror (NAM) window structure. A laser beam, generated in the center, planar waveguide section, leaves the waveguide at the bend, continuing substantially unabsorbed and undeflected through the wider bandgap cladding layer material towards the mirror facet. An amphoteric dopant, used during growth of the layered waveguide structure, causes a reversal of the conductivity-type within the semiconductor material deposited above inclined surface regions.

Abstract: A wafer structure and a method of making the same, upon which semiconductor devices may be formed, comprises first and second wafers. The first wafer comprises a first substrate having a thin oxide layer formed on a bottom surface thereof, the first substrate having a characteristic thermal expansion coefficient. The second wafer comprises a second substrate having an insulation layer formed on a top surface thereof, the insulation layer having a characteristic thermal expansion coefficient substantially matched with the characteristic thermal expansion coefficient of the first substrate and further having a high thermal conductivity. The second wafer further comprises a thin oxide layer formed on a top surface of the insulation layer, wherein the first thin oxide layer of the first wafer is bonded to the second thin oxide layer of the second wafer.

Abstract: An improved NPN transistor and method of building thereof includes: a P- substrate 50; a N+ buried region 52 provided therein; a N- epitaxial layer 56 deposited onto the N buried region; a P base diffusion region 66 in the N- epi layer; a N+ reach-through region 60 through the N- epi layer to the N+ buried layer to thereby define a collector; a N++ implant or diffusion region 102 provided in the P base diffusion region to thereby define an emitter; and a P++ implant region 74 provided around the N++ emitter implant region which thereby defines the extrinsic base of the transistor, wherein the P++ implant region extends through the P region into the N- epi layer and wherein the P++ implant region extends as close to the N++ emitter implant region as possible without encroaching on the emitter.

Abstract: A hardware simulator comprises a plurality of interconnected programmable logic devices (20) which are connected via a data bus (22) and a control bus (24). Address signals on control bus (24) are read by an interconnect logic block (18) associated with each device to selectively link the output latches and input latches of the devices (20) to the data bus (22). Accordingly, a series of signal transfers is carried out between the devices simulating the hardware. The interconnect logic blocks may be programmed to provide whatever connections between devices are required.