Abstract: A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices.

Abstract: A method of depositing Ge on a Si substrate in a reaction chamber includes the steps of: precleaning the substrate; evacuating the chamber to a pressure below 10.sup.-9 Torr; heating the substrate to 300-375 degrees C; and providing a 10% GeH4, 90% He mixture of gas with a GeH.sub.4 partial pressure of 1-5 mTorr.

Abstract: A method of forming patterned films on a semiconductor substrate 10 includes the steps of depositing a hardened photo resist underlay 30 onto the substrate, then depositing a polyether sulfone release layer 32, then depositing a photo sensitive resist layer 34 and exposing an etching a metallization pattern 36, 38 to the substrate 10. The structure is then blanket deposited with a conductive layer 40 to thereby create a conductive contact stud 42. The film layer 40 and resist layer 34 are removed by dissolving the polyether sulfone layer 32 in an NMP solution and the photo resist underlayer 30 is then removed using a selective photo resist stripper composition.

Abstract: A method of forming a thin silicon SOI layer by wafer bonding, the thin silicon SOI layer being substantially free of defects upon which semiconductor structures can be subsequently formed, is disclosed.

Abstract: A method for isolating a film from a substrate 50 includes the steps of: providing an N+ layer 52 on the substrate 50; forming an insulation layer 54 onto the N+ doped layer 52; etching a pair of trenches 56, 58 through the insulation layer 52 to thereby form an isolation region 60 of insulation material; laterally etching a cavity 62 underneath the isolation region; and, forming a film 64 onto the isolation region.

Abstract: A method for isolating areas of silicon from a substrate 50 includes the steps of: providing a buried N+ region 52 in the substrate; forming an intrinsic epitaxial layer 12 onto the N+ region; etching trenches 18, 20 through the intrinsic epitaxial layer to thereby form a desired isolation region 16 of intrinsic epitaxial material; laterally etching a cavity 22 underneath the desired isolation region; and, forming an insulation layer 24 of insulation material along the bottom of the desired isolation region exposed by the former etching steps.

Abstract: An interferometer 10 for measuring the position of the process surface 21 of a substrate 20 includes a coherent light source 12 for providing a light beam 14 which is partially transmitted and partially reflected by a beam splitter 16. The reflected light beam 18 is reflected off of the process surface 21 and the transmitted light beam 30 is reflected off of a translator 32 which vibrates a predetermined distance at a predetermined frequency. The phase shift between the light beams 22, 31 reflected off of translator 32 and the process surface 21 is measured using a photodetector 24, which provides an output signal 26 to a feedback servo unit 28. The servo unit 28 provides an output signal 38 which controls the vibration of translator 32. The output signal 38 of servo unit 28 is also indicative of the position of the process surface 21.

Abstract: A method of forming patterned film onto a substrate includes the steps of: depositing a polyether sulfone release layer 50; depositing a photoresist underlayer 52; patterning a predetermined film pattern through the underlayer 52 and the polyether sulfone layer 50; depositing a film layer 60 onto the wafer, thereby forming a patterned film 62 on the substrate 10; weakening the mechanical bonding strength to the polyether sulfone release layer 50 by immersing it in NMP; stripping off layers 54 and 60 by applying an adhesive backed tape 64 to the top of the film layer and applying a pulling force; and, removing the polyether sulfone release layer 50 by immersing the wafer in a NMP bath.

Abstract: A method of controlling the interfacial oxygen concentration of a monocrystalline/polycrystalline emitter includes the steps of: passivating the monocrystalline silicon surface by immersing the wafer in a diluted HF acid solution; transferring the wafer into a high vacuum environment; heating the wafer to between 400.degree. and 700.degree. C.; exposing the monocrystalline silicon surface to a gas having a partial pressure of oxygen of between 10.sup.-5 to 1 Torr for between 1 and 100 minutes; and, depositing polysilicon onto the monocrystalline silicon surface.

Abstract: A liquid interface cooling chuck assembly 10 includes a clamping section 12 having a top surface 16 with three separate cooling circuit grooves machined therein and a bottom surface 64 having a double spiral cooling circuit machined therein. The clamping section 12 is soldered to the flat top surface 18 of the support section 14 which as a bottom surface having structural ribs machined therein. Liquid is provided to the three cooling circuits of clamping section 12 to provide a liquid interface between a wafer and the top surface 16 of the clamping section 12. A cooling fluid is also circulated through the bottom surface cooling circuit.

Abstract: An analog to digital convertor (20) comprises an amplifier (100) for amplifying an analog input signal to generate an amplified output signal. A conversion means (110) periodically samples the amplified output signal to generate a digital word as a function of each sample. A compensation means, preferably including a microcontroller logic circuit (130), compensates for drift in the output signal steady state level of the amplified output signal. The compensation means includes a tracking means (130) for summing a digital offset value and the digital word in response to, and to compensate for, the drift in the output signal level between upper and lower limits. The compensation means also includes a bias means (130,140) for changing a bias signal level at the input of the amplifier (100) in response to, and to compensate for, the drift extending beyond the limits.

Abstract: A vertical isolated-collector PNP transistor structure (58) comprises a P+ region (45), a N region (44) and a P- well region (46) which form the emitter, the base and the collector, respectively. The P- well region is enclosed in a N type pocket comprised of a N+ buried layer (48) and a N reach-through region (47) in contact therewith. The contact regions (46-1, 47-1) to the P- well region (46) and to the N reach-through region (47) are shorted to define a common collector contact (59). In addition, the thickness W of the P- well region (46) is so minimized to allow transistor action of the parasitic NPN transistor formed by N PNP base region (44), P- well region (46) and the N+ buried layer, (48) respectively as the collector, the base and the emitter of said PNP transistor. The PNP transistor structure (67) may be combined with a conventional NPN transistor structure (61).

Abstract: An electrostatic chuck 40 assembly includes, from top to bottom: a top isolation layer 42; an electrostatic pattern layer 44 comprised of an electrically conductive electrostatic pattern 46 disposed on a substrate 45; a heating layer 50 comprised of an electrically conductive heating pattern 54 disposed on a substrate 52; a support 60; and, a heat sink base 70 having backside cooling and insulating channels 78, 80 provided therein.

Abstract: A DC-to-DC converter is operated in accordance with a predetermined primary circuit ON time and a sensed predetermined secondary circuit current level to provide improved charging performance and extended battery life. Energy is stored in the primary of a coupled inductor when power in the primary, provided by a battery having an internal impedance which varies over the battery's lifetime, is switched ON for a predetermined time t.sub.ON. Upon expiration of time t.sub.ON, power is switched OFF, whereupon stored energy is transferred to the secondary via a flyback type process, thus charging a storage capacitor. A preventing means prevents a premature switching ON of power in the primary subsequent to the expiration of time t.sub.ON. The energy storage cycle repeats when current sensed in the secondary decreases below a predetermined minimum current threshold.

Abstract: In a flyback type self-oscillating DC-to-DC converter, a voltage sensing means indirectly senses the storage capacitor voltage and indicates when the voltage across a storage capacitor has been charged to a predetermined charged value. The voltage sensing means comprises a voltage dividing resistor having a tap intermediate the ends thereof and being connected across a primary winding of a coupled inductor of the DC-to-DC converter. The voltage across the primary winding corresponds to a voltage on the storage capacitor according to the turns ratio of the primary winding to a secondary winding during a measurement period, the measurement period having first and second portions. A comparing means compares a voltage at the tap of the voltage dividing resistor with a predetermined reference voltage and provides an output signal having first and second conditions when the tap voltage is below or above, respectively, the predetermined reference voltage.

Abstract: A flexible printed wiring arch connector, having first and second sets of finger-like projections integrally formed on opposite sides of an elongated substrate, is adapted to be inserted and flexibly secured into corresponding apertures of a receiving printed circuit board. A plurality of electrical conductors are formed on the substrate along the elongated dimension thereof. Connector leads, formed on the finger-like projections, are electrically connected to desired individual ones of the conductors and extend in a direction generally perpendicular to the conductors. Arcuate bending of the projections and connector leads in a direction crosswise of the elongated substrate disposes the projections and connector leads for insertion and retention under a restoring spring force in the circuit board apertures. Once flexibly secured in place, the flexible printed wiring arch connector is ready for soldering.