Abstract: A technique for improving the performance of head alignment during reading of data from and writing data to a tape medium. An apparatus controls writing of data by a tape drive that drives a tape medium in both forward and reverse directions to record data. The apparatus includes a position obtaining unit that obtains the current position of the head of the tape drive with respect to the tape medium, a determining unit that determines whether the current position of the head is within a predetermined range on the tape medium, a generating unit that generates dummy data in response to determination that the current position of the head is not within the predetermined range, and a write control unit that writes dummy data on the tape medium until the current position of the head is within the predetermined range on the tape medium.

Abstract: An interface system is provided between a source component (210) and a destination component (220) having multiple parallel lines for transmitting data or parity bits (231-234, 251-253) and one or more spare lines (241-243). An error detection means (222) identifies one or more faulty lines. A mapping means (228) re-routes data or parity from a faulty line to a spare line. A communication link (208) is provided for communicating the re-routing between the source component (210) and the destination component (220). The error detection and mapping can be repeated to detect and re-route sequential multiple-bit line errors using additional spare lines (241-243).

Abstract: A method for reducing the power consumption of a register file of a microprocessor supporting simultaneous multithreading (SMT) is disclosed. Mapping logic and associated table entries monitor a total number of processing threads currently executing in the processor and signal control logic to disable specific register file entries not required for currently executing or pending instruction threads or register file entries not meeting a minimum access threshold using a least recently used algorithm (LRU). The register file utilization is controlled such that a register file address range selected for deactivation is not assigned for pending or future instruction threads. One or more power saving techniques are then applied to disabled register files to reduce overall power dissipation in the system.

Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable.

Abstract: A semiconductor chip subdivided into power domains, at least one of the power domains is separately activated or deactivated and at least a part of the scannable storage elements are interconnected to one or more scan chains. At least one scan chain is serially subdivided into scan chain portions and the scan chain portion is arranged within one of the power domains. For at least one scan chain portion a bypass line is provided for passing by scan data and at least one select unit is provided for selecting between the bypass line and the corresponding scan chain portion in dependence of the activated or deactivated state of the corresponding power domains.

Abstract: The invention relates to a wordline booster circuit, especially an SRAM-wordline booster circuit, comprising a driving element (20) for shifting a voltage level of a charge storage element (50) for storing a charge necessary to generate a boosted voltage (Vb), a feedback element (30) for controlling the switching state of a charging element (40), wherein the charging element (40) is actively switchable between a turned-off state during a first time interval and a turned-on state during a second time interval, and an output port (14) for supplying the boost voltage to at least one wordline-driver circuit (100) of a memory device (200). The invention relates also to an operation method for such a wordline booster circuit as well as a memory array implementation on an integrated circuit, especially an SRAM memory array, with a wordline booster circuit.

Abstract: A methodology and implementation of a load-tagged pointer instruction for RISC based microarchitecture is presented. A first lower latency, speculative implementation reduces overall throughput latency for a microprocessor system by estimating the results of a particular instruction and confirming the integrity of the estimate a little slower than the normal instruction execution latency. A second higher latency, non-speculative implementation that always produces correct results is invoked by the first when the first guesses incorrectly. The methodologies and structures disclosed herein are intended to be combined with predictive techniques for instruction processing to ultimately improve processing throughput.

Abstract: A structure and method to reduce leakage of a Static Random Access Memory (SRAM) array, wherein the array is subdivided into a set of sub-arrays, whose supply voltages can be controlled independently using a single voltage regulation circuit dedicated to the entire SRAM array. A switch fabric enables independent switching of individual sub-arrays between a virtual ground level and a system ground level based on whether the sub-array is operating in power saving mode or a high performance mode to reduce leakage current when a sub-array is configured in a power saving mode.

Abstract: The object of the present invention is to provide a DRAM, in which the operation speed for a sense amplifier can be increased. Bit line precharging circuits PCt and PCb are arranged to precharge bit lines BLt and /BLt to a ground voltage GND, and reference word lines RWLo and RWLe and reference memory cells RMC are arranged, so that when a word line WL is activated, a potential difference is always generated between the bit lines BLt and /BLt. The sources of transistors N10 and N11 of an N-type sense amplifier NSAt are connected directly to a ground terminal GND, and the sources of transistors P2 and P3 of a P-type sense amplifier PSA are connected directly to a power source VDD. The gates of the transistors N10 and N11 are connected to the bit lines /BLt and BLt, and the drains are connected to the bit lines BLt and /BLt, respectively. Shift word lines SWL and shift memory cells SMC are arranged, so that the N sense amplifier NSAt can amplify the potential difference between the bit lines BLt and /BLt.

Abstract: A method of diagnosing semiconductor device functional testing failures by combining deterministic and functional testing to create a new test pattern based on functional failure by determining the location of the type of error in the failing circuit. This is accomplished by identifying the failing vector during the functional test, observing the states of the failed device by unloading the values of the latches from the LSSD scan chain before the failing vector, generating a LOAD from the unloaded states of the latches, applying the generated LOAD as the first event of a newly created independent LSSD deterministic pattern, applying the primary inputs and Clocks that produced the failure to a correctly operating device, unloading the output of the correctly operating device to generate a deterministic LSSD pattern; and applying the generated deterministic LSSD pattern to the failing device to diagnose the failure using existing LSSD deterministic tools.

Abstract: The present invention relates to a method for routing data paths in a semiconductor chip with a plurality of layers. The inventive method comprises the steps of wiring a launching clock path and a receiving clock path on one or more layers according to at least one predetermined condition, performing one or more timing tests for determining any critical paths, and determining a weight function for every layer of each critical path. Said weight function is defined as the difference between a property of the launching clock tree and the same property of the receiving clock tree on said layer. If said weight function is positive for any layer, the wiring of the data path is not allowed on said layer. Preferably the remaining layers are chosen in such a way that a local variation of the delay on said layer is minimal.

Abstract: A method for performing a common cancel (CC) function on a dynamic random access memory (DRAM) semiconductor device to improve reliability and speed of a memory system. The CC function rakes advantage of the intrinsic delays associated wit memory read operations at high clock frequencies, and the increased write latency commensurate with increased read latencies where non-zero larencies for read and write operations are the norm by permitting address and command ECC structures to operate in parallel with the address and command re-drive circuitt The CC function is extendable to future DDR2 and DDR3 operating requirements in which latency of higher frequency modes will increase due to the shift from 2 bit pre-fetch to 4 and 8 bit pre-fetch architecture.

Abstract: A memory system including a bus 10, 11, a memory 17, a memory controller 16, a first device 13 having a cache, and a second device 15, all connected to the bus, wherein the memory controller includes a buffer 20 for temporarily storing cache data and write data that the second device writes in the memory. The buffer of the memory controller temporarily stores cached data and the write data to be written on write access to the memory by the second device, which enables maintenance of data coherency while avoiding a write access retry by the second device.

Abstract: To achieve, by a simple circuit configuration, a DRAM that permits refresh current to be effectively reduced by selectively setting refresh cycles. A memory cell array is divided into 64 subarrays, and each subarray is further divided into 8 blocks. A refresh cycle control circuit has a fuse circuit for setting a frequency dividing ratio of 1 or 1/2, a frequency divider that divides the frequency of a predecode signal by the set frequency dividing ratio, fuse circuits for setting a frequency dividing ratio of 1 or 1/4, and frequency dividers for dividing predecode signals by the set frequency dividing ratio. The refresh cycle control circuit is capable of setting a 64-ms or 128-ms refresh cycle for the 64 subarrays and a 64-ms or 256-ms refresh cycle for 512 blocks.

Abstract: A voltage translator circuit and a method for operating the same. The voltage translator circuit includes (a) an input node, an output node, and a ground node; (b) a voltage divider circuit including a first and second resistors coupled in series between the input node and the ground node; (c) a start voltage circuit coupled to a first voltage and to the input node; (d) a transfer circuit coupled to the output node; and (e) a capacitive circuit having a first and second capacitive nodes. The first capacitive node is coupled to the voltage divider circuit. The second capacitive node is coupled (i) to the first voltage via the start voltage circuit, and (ii) to the output node via the transfer circuit. In response to the input node changing towards the first voltage, the start voltage circuit is capable of disconnecting the second capacitive node from the first voltage.

Abstract: A computer system having a plurality of processors where each of the processors is dynamically assigned for execution of tasks based upon either performance or reliability.

Abstract: A fault recovery system for an array of memory cells. A register stores data indicating addresses of multi-cell fails and single-cell fails. A first fault correction system accesses data from the register to fix both multi-cell fails and single-cell fails. A second fault correction system does not access said register and fixes single-cell fails. During testing, if a multi-cell fail is detected the register stores its address by deleting an address of a single-cell fail if the register is full.

Abstract: A power supply apparatus is provided, which reduces undershoot of a DC source voltage when a power supply interrupt occurs. The power supply apparatus supplies a DC voltage to an output of the power supply apparatus, an output capacitor is provided between the power supply output and ground, and a resistor controls the discharge time constant when the supply of source voltage is temporarily halted. The resistor is coupled in series with a switch, forming a discharge path to ground for the output capacitor. A discharge path switch disables the discharge path when source voltage is supplied. The discharge path is enabled in the event of a power supply interrupt and disabled during normal power supply operation.

Abstract: A low power oscillator circuit for a self-refresh timer in a memory array is disclosed. When a voltage (V1) of a comparison node (N1) exceeds a first reference voltage (Vref1), a differential amplifier (101) in an oscillator (1) causes a pulse generator (110) to output a pulse. A charge/discharge circuit (105) discharges the comparison node (N1) in response to pulse. In this event, a control circuit (4) disables a first control signal (CT1) to halt operation of the differential amplifier (101). When the voltage (V1) exceeds a second reference voltage (Vref2) equivalent to the sum of threshold voltages of a discharge circuit (43) in consequence of gradually charging the comparison node (N1) by the charge/discharge circuit (105) after it was discharged, the control circuit (4) activates the first control signal (CT1) to operate the differential amplifier (101).

Abstract: Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.