Abstract: An electronic fuse structure is disclosed for integrated circuits that is programmable with low voltage and incorporates a differential sensing scheme. The programming step is performed at about 1.5 times Vdd while the sense operation is performed at Vdd, which limits the resistance variation through the electronic fuse caused by the sense operation. During the sense operation a gating transistor emulates the voltage drop across a fuse select transistor for the case of an intact fuse. A circuit and method for characterizing the resistance of the electronic fuse is also disclosed.

Abstract: To provide a DRAM that reduces access latency during refresh and performs refresh for any non-accessed bank in parallel with normal memory accesses. Furthermore, the DRAM allows access to a bank that is undergoing refresh. The DRAM includes a circuit for directing refresh execution by comparing bank address of both access and refresh operations, a circuit for specifying a bank address of the memory cells to be refreshed, a circuit for addressing a row address of the memory cells to be refreshed in the specified bank, a means for refreshing the memory cells, and a means for accessing the memory cells directly after refresh without denying the access request.

Abstract: Power is gated from global terrain to a voltage island while controlling leakage and managing transient power supply noise. The voltage island includes a field effect transistor (FET) power gate, a first connection to a global voltage source and a second connection to a disable signal source, and an island voltage net for supplying voltage to devices on the island. A power gate control circuit is responsive to the disable signal source for generating a test signal for selectively turning off the FET power gate as the disable signal source goes to a logical ‘1’, and for turning on the FET power gate as said disable source goes to a logical ‘0’. The FET power gate is responsive to the disable signal source being off for connecting the island voltage net to the global voltage source.

Abstract: The present invention relates to improvements in forming and transferring solder bumps for use in mounting integrated circuit substrates on chip carrier packages. A mold having cavities for the solder bumps is held in contact with a substrate and a compressible device. As the temperature is increased to melt the solder in the cavities, at an appropriate time and temperature, the compressible device is caused to decompress resulting in the mold separating from the substrate and leaving formed solder bumps on the contacts on the substrate. Various mechanisms are described to cause the force holding the mold and substrate together to decrease.

Abstract: The present invention discloses a memory, and a refresh method for memory, which performs a normal access and refresh one after another within one operation cycle of SRAM. The memory of the present invention comprises a refresh enable which directs execution of refresh, a row address counter that addresses a row address of memory cells to be refreshed, and an execution circuit which refreshes the memory cells of the addressed row address in response to the direction of execution of refresh.

Abstract: A fuse latch circuit with a current reference generator is described where the resistive switch point of the latch is stabilized against effects of manufacturing processing, operating voltage and temperature. A digital control word is used to select the desired resistive trip point of the fuse latch and compensation within the reference generator maintains this resistive trip point with high accuracy. The variable resistive trip point is set to a first value at test and then to a second value in use condition to enhance operating margin, and soft error immunity.

Abstract: A method and apparatus for implementing a recovery process for a resource manager. The method and apparatus has the resource manager take checkpoints in a manner such that in the case of failure of the resource manager, the time it takes to have requests processed again is shorter than a specified request processing time.

Abstract: A method and apparatus for analyzing an integrated circuit design for pnpn structures which are likely to latchup or cause injection of noise into the substrate. Once qualifying pnpn structures are identified, the method and apparatus automatically inserts a noise and latchup suppression circuit of the designers' choice into the pnpn structure to eliminate the latchup and/or noise concerns.

Abstract: A microprocessor, method and signal-bearing medium for storing a program for executing the method, includes a microcode unit for outputting control signals, for each of a plurality of instructions, required by the microprocessor for executing the instructions. The microcode unit includes an instruction address input for receiving an instruction address, a control variable input for receiving a control variable corresponding to a current state of the microprocessor, a control signal input for receiving all of the control signals output by the microcode unit for an immediately preceding instruction, and a plurality of embedded logic circuits each dedicated for evaluating one unique type of instruction received by the microcode unit.

Abstract: A programmable frequency divider circuit with symmetrical output is disclosed. The frequency divider includes a non-symmetrical LFSR based component operated in series with a symmetrical divider component. Both the LFSR and the symmetrical divider may be programmed to provide flexibility. The frequency divider can dynamically adjust the divisor of the LFSR component to overcome limitations in the divide resolution due to the series combination of dividers, providing even and odd divisor values. The divider architecture can also provide higher level functions, including synchronization of multiple divider outputs, dynamic switching of divisor values and generation of multi-phased and spaced outputs. The linear feedback shift register (LFSR) component includes a feedback logic network decomposed into multiple stages to realize a maximum latch-to-latch operational latency of one gate delay regardless of the size of the LFSR.

Abstract: A high-voltage input tolerant receiver capable of achieving power savings with less distortion of analog signals is disclosed. When an external signal ?C input from a PAD 2 is less than 3.6V, a p-channel MOS transistor P10 is turned off. As a result, a control signal ?E becomes 0V to turn on a p-channel MOS transistor P1. At this time, an intermediate signal ?D output from a clamp circuit 3 becomes equivalent to the external signal ?C, and is not distorted. However, when the external signal ?C exceeds 3.6V, the p-channel MOS transistor P10 is turned on, and a control signal ?F output from a differential amplifier 9 becomes 0V. As a result, the p-channel MOS transistor P1 is turned off, and a level keeper 6 is enabled. Since the level keeper 6 remains inactive until the external signal exceeds 3.6V, current flowing through the level keeper 6 can be reduced.

Abstract: A dynamic semiconductor memory device capable of reducing standby current is disclosed. In a standby mode wherein only a refresh operation is performed, a precharge/equalize signal is activated only during a predetermined period before a word line is activated so as to precharge a bit line pair to a voltage that is half a line voltage immediately before the word line is activated. In the standby mode, the bit line pair is electrically isolated from a regulator that generates a voltage that is half the line voltage except for the above predetermined period, thus preventing leakage current from flowing therebetween even if a defect in which the word line is shorted with the bit lines occurs.

Abstract: A DRAM and access method for DRAM with a high data rate in a random row access mode. The DRAM includes a plurality of memory blocks composed of a plurality of storage segments each with a series of main word lines and sub-word lines. Each memory block is decoded into multiple segments and the main word lines are activated to select a predetermined number of sub-word lines. A corner block is provided that contains a plurality of Z-lines for selecting one of the sub-wordlines and a plurality of segment select lines for selecting a specific memory segment by activating a local Z-line.