Abstract: A technique for coalesced Power Loss Recovery PLR status bits in an Error Correction Code ECC enabled flash memory.

Abstract: An apparatus and method to facilitate validation and/or test of serial interfaces by analyzing error event types based at least in part on a code-stamp, compare engine logic and a memory for error capture.

Abstract: A method and an apparatus for testing transmitter and receiver have been disclosed. One embodiment of the apparatus includes a plurality of multiplexers to select one of a positive and a negative transmitter pins, and a first comparator to compare a voltage of the selected pin with a first reference voltage to determine whether there is leakage at the selected pin. Other embodiments are described and claimed.

Abstract: Use of an import cache and/or an export directory with an agent within to respond to requests for data. The import cache stores data that has been imported through the agent. The export directory stores information related to data that has been exported through the agent. Because the import cache and the export directory only store data that has passed through the agent, not all data transferred within a system are tracked by a single import cache or export directory.

Abstract: A processor that includes a digital throttle to monitor the activity of the execution pipeline and to change a frequency of a first or second PLL clock within a single clock cycle based on a power state.

Abstract: The cache coherency protocol described herein can be used to maintain a virtual model of a system, where the virtual model does not change as the system configuration changes. In general, the virtual model is based on the assumption that each node in the system can directly communicate with some number of other nodes in the system. In one embodiment, for each cache line, the address of the cache line is used to designate a node as the “home” node and all other nodes as “peer” nodes. The protocol specifies one set of messages for communication with the line's home node and another set of messages for communication with the line's peer nodes.

Abstract: A method, system, and apparatus to reduce power consumption of a memory by actively asserting the CKE pin based at least in part on a LRU status of the rows in an active mode.

Abstract: A thermal management that redirects the target of read transactions from a thermally failed Dual Inline Memory Module (DIMM) in one mirror, to the corresponding DIMM in the other mirror. The memory controller or MCH would effectively bias the read transactions toward the mirror that is best able to respond based on thermal feedback. Likewise, this may be used as a temporary redirection that continues for only as long as was required to reduce the operating temperature in the failing DIMM.

Abstract: A system for delivering power to a device in a specified voltage range is disclosed. The system includes a power delivery network, characterized by a response function, to deliver power to the device. A current computation unit stores values representing a sequence of current amplitudes drawn by the device on successive clock cycles, and provides them to a current to voltage computation unit. The current to voltage computation unit filters the current amplitudes according to coefficients derived from the response function to provide an estimate of the voltage seen by the device. Operation of the device is adjusted if the estimated voltage falls outside the specified range.

Abstract: A mechanism is disclosed for determining a voltage at a device in a power delivery network. The mechanism includes determining an impulse response for the power delivery network, and tracking the current consumed by the device as it operates over a sequence of clock cycles. The activity profile is filtered using a representation of the impulse response to provide a profile of the voltages at the device.

Abstract: Embodiments are disclosed in which two-dimensional image compression, such as for bi-level images, is implemented.

Abstract: A schematic, system, and flowchart to facilitate storage of directory information for a cache coherency protocol. The protocol allows for at least a single bit of directory information overwriting data stored in a cache coherency unit based at least in part on at least one status bit stored in a storage unit. Likewise, the cache coherency protocol determines whether the cache shared.

Abstract: An efficient invention for opening two pages of memory for a DRAM are discussed.

Abstract: An apparatus according to an embodiment of the present invention is disclosed. The apparatus includes a memory interface. The memory interface determines an access time of an original read request. The memory interface outputs a data ready signal when the access time of the original read request expires. An arbiter is coupled to the memory interface. The arbiter arbitrates access to the memory interface. A blocking unit is coupled to the memory interface. The blocking unit blocks a retry of the original read request from reaching the arbiter unit until the data ready signal is output by the memory interface. According to one embodiment of the memory controller a bus interface is coupled to the memory interface. The bus interface issues a deferred read signal to the device making the original read request upon receiving a signal from the arbiter.

Abstract: In accordance with one embodiment of the invention a circuit includes a split delay-chain, a phase detector, and a voltage controlled oscillator (VCO) coupled so as to produce a clock signal based on a non-external reference.

Abstract: Briefly, in accordance with one embodiment, an integrated circuit includes a phase-frequency detector (PFD) including two clock input ports, an up signal port and a down signal port. The PFD includes digital circuitry including transistors coupled in a configuration to adjust an amount of overlap of an up output signal pulse and a down output signal pulse based, at least in part, upon the magnitude of an amount of phase delay between two respective clock signal pulses applied to the two input ports. Of course, additional embodiments are also disclosed.

Abstract: An apparatus with a generator to generate a pattern and multiple scan chains configured to receive the pattern from the generator. Multiple signature registers coupled to the scan chains, to receive an output of at least one of scan chains during a mode of the integrated device.

Abstract: Hardware or software to test a circuit with a set of functional vectors. The invention compares expected results of functional vectors with the actual results of the test circuit. If there is a miscompare, a recursive comparison is done prior to the first clock cycle of the miscompare.

Abstract: A circuit comprising a first register and a second register to store the first and second status of the plurality of memory banks. Also, the circuit comprises a logic and an encoder circuit. The logic is coupled to the first and second registers and generates a third status of the plurality of memory banks based on the first and second status. The encoder coupled to the logic generates a refresh request in response to the third status of the plurality of memory banks.

Abstract: The present invention provides a mechanism for adjusting the activity of an integrated digital circuit such as a processor to reduce voltage changes attributable to current changes triggered by clock gating. The processor includes one or more functional units and a current control circuit that monitors activity states of the processor's functional units to estimate the current consumed over n clock cycles. The current control circuit estimates the current change for a given clock cycle from the n activity states and compares the estimated current change with first and second thresholds. The processors activity is decreased if the estimated current change is greater than the first threshold, and the processor activity is decreased if the estimated current change is less than the second threshold.