Patents Represented by Attorney Michael J. Nesheiwat

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  • Circuit and method for merging refresh and access operations for a memory device
    Patent number: 6463001
    Abstract: A memory controller to generate refresh requests for by storing the status of memory rows and an arithmetic logic unit to store a second status of all the memory rows of all the memory devices in the system memory configuration. A second logic unit stores the open status of the plurality of memory banks. The third logic generates a refresh request based on the open status and the second status in response to a refresh frequency.
    Type: Grant
    Filed: September 15, 2000
    Date of Patent: October 8, 2002
    Assignee: Intel Corporation
    Inventor: Michael W. Williams
  • Method and apparatus for integrated flip-flop to support two test modes
    Patent number: 6446229
    Abstract: A circuit, an integrated flip flop, to receive an input in response to a clock signal. The integrated flip flop has a first and second slave latch and a master latch. The first slave latch receives an output from the master latch in response to the clock signal and a control signal for a first test mode of operation. The second slave latch receives an output from the master latch in response to the clock signal in one of a second test mode of operation or a normal functional mode of operation.
    Type: Grant
    Filed: June 29, 2000
    Date of Patent: September 3, 2002
    Assignee: Intel Corporation
    Inventors: Dale F. Merrick, Joachim Priesnitz