Abstract: Various systems and methods for equation graphing are disclosed herein. For example, some embodiments of the present invention provide methods for graphing equations in a substantially real time environment. Such methods include receiving a first equation and a second equation, and parsing the equations such that they are each formatted in a common format. In addition, the first parsed equation is reduced to one or more first equation shapes that provide a graphical representation of the first equation. A determination is made abut whether a real time control has been satisfied. Where the real time control has been satisfied, the first equation shapes are painted to a display prior to reduction of the second parsed equation to one or more second equation shapes.

Abstract: A method and apparatus for decoding digital quadrature phase shift keying data includes converting and intermediate frequency signal from an analog signal to a digital signal and digitally processing the digital signal to detect and decode the digital quadrature phase shift keying and extract encoded data.

Abstract: Beat matching for two audio streams extracts beats from each, computes a conversion ratio from one stream to the other stream by an initial beat alignment plus a stability-maintaining beat alignment. A variable resampling converter or time scale modifier adjusts one stream to align beats with those of the other (reference) stream. Thus for cross-fading two music streams the beats of the fading-in stream can be matched to those of the fading-out stream for a seamless transition.

Abstract: A system comprises a storage cell coupled to multiple bitlines and a transistor that couples to the multiple bitlines in parallel with the storage cell. The transistor is activated while the storage cell is read.

Abstract: Reducing electromagnetic radiation from semiconductor devices. At least some of the illustrative embodiments are methods comprising driving a Boolean state to a signal pad of a semiconductor device (the driving through a transistor with a first drain-to-source impedance during the driving), and maintaining the Boolean state applied to the signal pad through the transistor with a second drain-to-source impedance, higher than the first drain-to-source impedance.

Abstract: A file archive system for storing multiple files and directories as a single file. The file archive system could be used on a hand-held computer or other computing device. The file archive system in a preferred embodiment has an operating system with a loadable file system. In another embodiment, the file archive system includes a file archive structure for storing multiple files as a single file.

Abstract: Stabilization for devices such as hand-held camcorders segments a low-resolution frame into a region of reliable estimation, finds a global motion vector for the region at high resolution, and uses the global motion vector to compensate for jitter.

Abstract: A holdover circuit is configured with a holdover capacitor, preferably an aluminum electrolytic capacitor, to provide uninterruptible operation for an electrical load operable over a limited range of input voltage during brief power interruptions. The holdover circuit includes a switching regulator configured with two active switches that are controlled with complementary duty cycles to charge and discharge the holdover capacitor at a voltage higher than the voltage of the load. The controller for the switching regulator may be configured to regulate the voltage of the holdover capacitor at a voltage proportional to the load voltage or at a constant voltage. The controller for the switching regulator is configured to operate in different modes during normal powered operation and during holdover.

Abstract: A digital down converter (DDC) can be provided in a digital radio receiver front end to produce baseband I and Q signals using mixing, decimating and narrow and wide filtering dependent upon the nature of the signals. After receiving a single wide IF signal from the IF tuner, a single IF ADC converts the IF signal to digital form, and the DDC generates wide and narrow baseband I and Q signals for digital signal processing. The DDC passes wide baseband I and Q signals to a digital baseband processor, while narrow baseband I and Q signals are passed to the analog baseband processor. The system and method of the present invention permits more accurate filtering of the respective digital and analog signals, while reducing receiver complexity and cost. An analog filter in the digital radio tuner can have relaxed specifications permitted by the DDC according to the present invention.

Abstract: An ultra low power relaxation CMOS oscillator for low frequency clock generation comprises a current source and a pair of capacitors that are alternatingly charged by the current source and discharged by thyristor-based inverters being used as comparators. No separate bias currents are needed.

Abstract: A digital processor (2, 102) for use in a digital controller (10) is disclosed. The digital processor (2, 102) includes a coefficient product memory (22) that stores previously calculated products of filter coefficients and each of a set of available input values. The memory (22) is addressed according to a received input value, and outputs a plurality of coefficient products associated with that input value. These coefficient products are combined across time samples (with one or more coefficient products delayed for use in later cycles), to produce an output value. The digital processor (2) can be used in combination with an analog-to-digital converter (4) and a pulse-width modulated circuit (6) to control a power supply. According to another embodiment of the invention, comparators (62H, 62L) and a counter (66) can be used instead of the analog-to-digital converter, for additional efficiency.

Abstract: Beat matching for two audio streams extracts beats from each, computes a conversion ratio from one stream to the other stream by an initial beat alignment plus a stability-maintaining beat alignment. A variable resampling converter or time scale modifier adjusts one stream to align beats with those of the other (reference) stream. Thus for cross-fading two music streams the beats of the fading-in stream can be matched to those of the fading-out stream for a seamless transition.

Abstract: The client loads an application class through a gateway server that preloades and preresolves a class, creates a binary representation of new portions of the preloaded and preresolved class, and sends only the new portion to the client.

Abstract: A system to reduce noise includes a noise measurement device that provides a measure of noise associated with a digital input video signal. A noise reduction filter provides a noise-reduced digital output video signal corresponding to the luma and chroma of the digital input video signal. The noise reduction filter has a parameter that varies on a pixel basis for the component of the digital input video signal as a function of the measure of noise. The range and sensitivity of the noise reduction can be user programmable.

Abstract: Low-complexity synthesis filter bank for MPEG audio decoding uses a factoring of the 64×32 matrixing for the inverse-quantized subband coefficients. Factoring into non-standard 4-point discrete cosine and sine transforms, point-wise multiplications and combinations, and non-standard 8-point discrete cosine and sine transforms limits memory requirements and computational complexity.

Abstract: An emulation system that allows a user to create a script is provided. The emulation system emulates a handheld computing device, such as a calculator, on an electronic device such as a personal computer. The script, which includes an input sequence, may be recorded and played back at a later time. In a preferred embodiment, annotations may be added to the script to help explain the concepts being illustrated by the script. The annotation may include text, graphics, audio, and/or video. Upon playback, the input sequence recorded in the script is used as input to the emulator. The playback may be automated or performed one step at a time, thereby allowing the student to step through the script and study intermediate results. The input sequence may represent, for example, digits, commands (e.g., store, recall, graph, list, print, etc.), or functions (e.g., x2, x3, compute, tan, sin, cos, etc.).

Abstract: A method for generating and evaluating a table model for circuit simulation in N dimensions employing mathematical expressions for modeling a device. The table model uses an unstructured N-dimensional grid for approximating the expressions.

Abstract: A delay locked loop includes a storage element coupled to a data bus and produces a data synchronization signal. A phase detector receives a data clock signal and the data synchronization signal and produces a delay control signal. A first delay circuit produces a signal which is delayed relative to the data clock signal according to the delay control signal. A second delay circuit receiving the delayed signal produces a control signal coupled to a control input of the storage element by delaying the delayed signal an amount which causes the control signal to have a predetermined duty cycle.

Abstract: A method of determining the degree of calibration of an RTP chamber (1) includes providing a test wafer having a deposited sichrome layer (22) of sheet resistance Rsi on an oxide layer (21) formed on a silicon substrate (20). The test wafer is annealed in the RTP chamber for a selected duration at a selected anneal temperature which is measured by the a permanent thermocouple or pyrometer (8). The sheet resistance of the annealed sichrome is measured, and a sheet resistance change ?Rs=Rsi?Rsf is computed. The “actual” value of the anneal temperature is determined from predetermined characterizing information relating ?Rs to a range of values of anneal temperature. The RTP chamber is re-calibrated if in accordance with the value of ?Rs if the difference between the “actual” value of the anneal temperature and the value measured by the permanent thermocouple or pyrometer exceeds an acceptable error.

Abstract: A syndrome evaluation with partitioning of a received block of symbols into subsets and interleaved partial syndrome evaluations to overcome multiplier latency. Parallel syndrome evaluations with a parallel multiplier.