Abstract: A method and apparatus improves the stability and noise performance of frequency synthesis and synchronization circuits. A cancellation circuit provides an error signal that is a measure of integrated quantization error in a delta-sigma modulator that controls the ratiometric division factor in a fractional-N phase-lock loop (PLL). The error signal is fed to the loop filter of the phase-lock loop as a correction signal via a differentiator (high-pass filter). The high pass filter removes substantially all in-band components from the cancellation signal, which reduces the linearity requirement on the cancellation signal path. The cancellation signal can be tapped from an internal numerical integrator of the delta-sigma modulator that is then converted to an analog signal, that is then filtered and combined with the phase comparator output in the loop filter.

Abstract: A method and system for providing performance estimations for a specified power budget provides an indication of the impact on processing performance when closed-loop power/performance control is employed to meet the specified power budget. A workload, which may be the actual workload, or a test workload is run to determine actual power consumption at intervals during the execution of the workload. The power values are examined and if they exceed the specified budget, which may be one of multiple possible budget values, an estimate of the amount by and duration for which the closed-loop power/performance control would have to reduce the performance of the system for each interval in order to provide an estimate of actual performance for the budgetary level(s). The estimate is informed by tests of the workload at each power/performance level to provide a non-linear estimate of the relationship between performance and power for the particular workload.

Abstract: A method and apparatus for measuring communications link quality provides accurate on-chip estimation of the difficulty of achieving a particular bit error rate (BER) for a communications link. A low cost/complexity accumulator circuit connected to internal signals from a clock/data recovery (CDR) circuit provides a measure of high frequency and low frequency jitter in a received signal. The low frequency jitter measurement is used to correct the high frequency jitter measurement which may otherwise contain error. The corrected output may be used to adjust operational characteristics of the link or otherwise evaluate the link for operating margin. The correction may be performed by subtracting a portion of the low frequency jitter measurement from the measured high frequency jitter, or the value of the low frequency jitter measurement may be used to select between two or more correction factors that are then applied to the high frequency jitter measurement.

Abstract: A processor including a register file and method for computing flush masks in a multi-threaded processing system provides fast and low-logic-overhead computation of a flush result in response to multiple flush request sources. A flush mask register file is implemented by multiple cells in an array where cells are absent from the diagonal where the column index is equal to the row index. Each cell has a vertical write enable and a horizontal write enable. When a row is written to validate that row's tag value, the column having an index equal to the row selector is automatically reset (excepting the absent cell mentioned above) . On a read of a row, a wired-AND circuit provided at each column provides a bit field corresponding to other rows that have been written since a last reset of the row, which is a flush mask indicating newer tags and the selected tag.

Abstract: A circuit for computing moment pre-products for statistical analysis reduces data transfer volume for on-chip statistical measurements. The circuit calculates the sums of multiple exponentiations of outputs of one or more measurement circuits, thereby reducing the amount of data that must be transferred from a wafer. An integer scaling of the input data is arranged between zero and unity so that the exponentiations all similarly lie between zero and unity. The circuit can use look-up tables and adder/accumulators to accumulate the contributions of each measurement to each exponentiation, or use a multiplier arrangement to determine the contributions. The multipliers can be implemented in the adder/accumulators by clocking the adder/accumulators by corresponding counts determined from the measurement data and lower-order exponentiations. Ranges of the measurement values are determined by capturing maximum and minimum values using comparators as the measurements are input.

Abstract: A pre-charge apparatus and method for controlling startup transients in a capacitively-coupled switching power stage provide lower cost and improved startup transient performance in Class D amplifiers, as well as in other AC power converter applications. A charging source is activated at startup to control the charging of an external capacitor from a single power supply rail to an operating point voltage equal to the average DC output of the switching circuit, while a control circuit disables the output power stage of the switching converter. The current source may be a constant-current source and/or may be controlled via feedback from the voltage or current at the output terminal of the converter to taper the current level to more accurately control the charging. A discharge circuit can also be provided to discharge the output terminal to an opposite power supply rail before commencing the controlled charging.

Abstract: A delta-sigma modulator coefficient calibration method and apparatus provides for adjustment of the modulator coefficients, and thus the modulator noise transfer function (NTF), in operational environments. A noise signal is injected into the feedback loop of the delta-sigma modulator either before or after the quantizer and the output of the modulator is correlated with the noise signal. The delta-sigma modulator has adjustable coefficients that are adjusted in conformity with the correlator output to achieve a more desirable noise transfer function. The correlator may include a tapped delay line and multiple correlators for simultaneously measuring each modulator coefficient directly, or may include a variable delay and a single correlator for measuring each coefficient sequentially.

Abstract: A three-dimensional imaging resonator and method therefor provides improved surface height measurement capability in optical measuring systems. A resonator including a surface of interest in a resonant image path is coupled to an external multi-pixel detector that detects an image of intensity of light reflected from or transmitted through the resonator. An imaging system is included in the resonator to image a region of a surface of interest on another reflector forming part of the resonator. By changing an effective cavity length of the resonator, the image is “scanned” in a direction perpendicular to the other reflector and a processing system stores information corresponding to resonance peaks to achieve a mapping of feature height above the surface of interest. The resonator effective cavity length can be changed by sweeping the illumination wavelength or by mechanically or otherwise altering the optical length of the resonator.

Abstract: A resonator method and system for distinguishing characteristics of surface features or contaminants provides improved inspection or surface feature detection capability in scanning optical systems. A resonator including a surface of interest in the resonant path is coupled to a detector that detects light leaving the resonator. Changes in the resonance peak positions and peak intensities are evaluated against known changes for standard scatters in order to determine the material characteristics of an artifact at the surface of interest that causes a resonance change. The lateral size of the artifact is determined by de-convolving a known illumination spot size with the changing resonance characteristics, and the standard scatterer data is selected in conformity with the determined artifact size.

Abstract: A method and system for modifying the content of e-mail transmissions based on customization settings determines when an e-mail user has customized an e-mail message and prompts the user to accept or reject automatic modification of the e-mail message text to indicate a particular customization settings. The e-mail program checks the customization settings, then the e-mail program prompts the user if a customization is set for which a text modification can be automatically made. For example, a “cc:” list may be added to the message text in response to the checking detecting a list of copied recipients. The e-mail program may further parse the message text in order to avoid prompting the user to add text associated with a customization for which the user has already made an indication within the message content (message body, subject line, et cetera).

Abstract: An extended dynamic range consecutive edge modulation (CEM) method and apparatus provides improved dynamic range in a noise-shaped CEM pulse generator. A limiting circuit is provided to adjust the rising and trailing edge pulse portion widths to correct conditions where a minimum high-state or low-state pulse width would be violated by the commanded output value of the noise-shaping modulator. The adjusting circuit delays the rising edge of the next pulse if the minimum low state pulse width would not be met and/or extends the falling edge portion of the next pulse if the minimum high-state pulse width would not be met. The modulation range may be wider than typically possible for linear operation and may be set to ranges exceeding one-hundred percent modulation. The adjusting circuit overrides commanded modulation values during a next pulse if combination with the previous pulse will cause violation of a minimum pulse width.

Abstract: A dynamic logic circuit apparatus and method for reducing leakage power consumption via separate clock and output stage control reduces power consumption of processors and other systems incorporating dynamic circuits. The power control signal may be a delayed version of the logic clock and turns on the output inverter foot device after the dynamic node has had sufficient time to evaluate, providing a fast evaluate time and reducing leakage through the inverter input when the foot device is off. Alternatively, a coarsely timed static power control signal may be used to control the inverter foot devices. The drains of the inverter foot devices can be commonly connected across multiple circuits, reducing the foot device total area.

Abstract: A method and system for energy management in a simultaneous multi-threaded (SMT) processing system including per-thread device usage monitoring provides control of energy usage that accommodates thread parallelism. Per-device usage information is measured and stored on a per-thread basis, so that upon a context switch, the previous usage evaluation state can be restored. The per-thread usage information is used to adjust the thresholds of device energy management decision control logic, so that energy use can be managed with consideration as to which threads will be running in a given execution slice. A device controller can then provide for per-thread control of attached device power management states without intervention by the processor and without losing the historical evaluation state when a process is switched out. The device controller may be a memory controller and the controlled devices memory modules or banks within modules if individual banks can be power-managed.

Abstract: A dynamic logic circuit incorporating reduced leakage state-retaining devices reduces power consumption of processors and other systems incorporating dynamic circuits. A keeper circuit provides a low leakage retention of the state of the output stage of the dynamic circuit so that an output circuit foot device can be disabled except when required for a transition in the output of the dynamic circuit. The keeper circuit includes a transistor having a smaller area than a corresponding transistor in the output circuit, thus reducing leakage through the gate of the output circuit when the keeper circuit is holding the output and the output circuit foot device is disabled. A self-clocked control of the output circuit foot device can be provided via a delayed version of the dynamic logic gate output, or may be provided by an external control circuit that generates a delayed version of the precharge clock or a multi-cycle signal.

Abstract: A phase-measuring delta-sigma modulator calibration method and apparatus provides for adjustment of the modulator noise transfer function (NTF) of the modulator in operational environments. A signal is injected into the feedback loop of the delta-sigma modulator either before or after the quantizer and the phase of the noise transfer function is measured by phase comparing the injected signal and quantizer output, which is first filtered with a narrow-band filter to remove other quantization noise or signal components. The delta-sigma modulator has adjustable coefficients that are adjusted in conformity with the phase-measurement to achieve a more desirable noise transfer function. Quadrature detection may be employed, with filtering provided by digital filters already present in an ADC converter for output filtering, or accumulators may be included to perform the phase accumulation. The signal generation and phase measurement may be at the zero of the NTF.

Abstract: A method and system for short-circuit current modeling in CMOS circuit provides improved accuracy for logic gate power dissipation models in computer-based verification and design tools. The model determines the short circuit current for each complementary pair within a CMOS circuit. Input and output voltage waveforms provided from results of a timing analysis are used to model the behavior one device of the complementary pair. The device is selected as the limiting device (the device transitioning to an “off state) from the direction of the logic transition being modeled, which is also the device that is not charging or discharging the output load. Therefore, the current through the selected device can be determined from the input and output waveforms and is equal to the short-circuit current prior to the saturation of the selected device.

Abstract: An on-wafer method and apparatus for preprocessing measurements of process and environment-dependent circuit performance variables provides new techniques for yield/performance test and analysis. An on-wafer circuit calculates the sums of multiple exponentiations of outputs of one or more measurement circuits, thereby reducing the amount of data that must be transferred from the wafer without losing information valuable to the analysis. An integer scaling of the input data is arranged between zero and unity so that the exponentiations all similarly lie between zero and unity. Measurement value ranges are determined by capturing extreme values using comparators as the measurements are input.

Abstract: A centered-pulse consecutive edge modulation (CEM) method and apparatus provides a pulse output that advantageously exploits the full edge update rate of the CEM while providing substantially centered pulses. The method and apparatus also operate without substantial delay in the input control path. The apparatus includes a delta-sigma noise shaping modulator followed by a CEM that receives an output of the delta-sigma modulator quantizer. A non-linear correction signal is applied with polarity alternating at each edge and is applied to the quantizer input or is designed into the quantizer transfer function. The non-linear correction signal compensates for the noise-shaping modulator output such that the expected rising edge and falling edge widths of the CEM output pulses are substantially equal with respect to a DC input to the delta-sigma modulator.

Abstract: A method and apparatus for maintaining an ideal frequency ratio between numerically-controlled frequency sources provides a mechanism for maintaining coherence between multiple synchronization references where a known ideal rational relationship between the sources is known. Multiple numerically controlled oscillators (NCOs) generate the multiple synchronization references, which may be clock signals or numeric phase representations and the outputs of the NCOs are compared with a ratiometric frequency comparator that determines whether there is an error in the ratio between the NCO outputs. The frequency of one of the NCOs is then adjusted with a frequency correction factor provided by the ratiometric frequency comparator. The NCO inputs can represent ratios of the synchronization reference frequencies to a fixed reference clock and the NCOs clocked by the fixed reference clock.

Abstract: A method and logical apparatus for switching between single-threaded and multi-threaded execution states within a simultaneous multi-threaded (SMT) processor provides a mechanism for switching between single-threaded and multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. Internal control logic controls a sequence of events that ends instruction prefetching, dispatch of new instructions, interrupt processing and maintenance operations and waits for operation of the processor to complete for instructions that are in process.