Abstract: A cascaded test circuit with inter-bitline drive devices for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A row in a memory array is enabled along with a set of drive devices that couple each bitline pair to the next in complement fashion to form a cascade of memory cells. The drive devices can be inverters and the inverters can be sized to simulate the bitline read pre-charge device and the write state-forcing device so that the cascade operates under the same loading/drive conditions as the operational with memory cell read/write circuits. The last and first bitline in the row can be cascaded, providing a ring oscillator or the delay of the cascade can be measured in response to a transition introduced at the head of the cascade. Weak read and/or weak write conditions can be measured by selective loading.

Abstract: A method and system for managing peripheral connection wakeup signaling in a processing system supporting multiple virtual machines provides a mechanism by which ownership of a peripheral having system wakeup capability is transferred between virtual machines. The power management event signal is connected to a service processor input that in turn signals a hypervisor to direct the wakeup activity to a particular logical partition in which the virtual machine was last executing. The hypervisor can then determine whether or not to wake up the entire system, or portions thereof and can direct the power management event to the appropriate virtual machine. In particular the peripheral may be an Ethernet adapter supporting Wake-On-LAN capability. State initialization, which is typically ensured by system power cycling is provided instead by controlling power to the standby power source or in some instances by forcing an indication of a disconnect/reconnect of the wakeup signaling connection.

Abstract: A method and apparatus for ameliorating the effects of noise generated by a bus interface provides improved performance of integrated circuits having other circuits sensitive to the transient noise introduced by bus signal switching. Additional signals are generated that equalize the frequency of occurrences of the transients, so that an effectively constant and non-data-dependent frequency is generated over the totality of the signals. The loading characteristics of the additional signals and interface signals are matched, and the interface and additional signals may be generated as complementary pairs, so that the net DC energy of the transients is also substantially made equal to zero. Any or all of the interface and additional signals may be used as data signals, or all but one of the signals may be supplied to an internal or external dummy load. A loading circuit may be calibrated by a circuit that senses the interface loading.

Abstract: A weighted event counting system and method for processor performance measurements provides low latency and low error performance measurement capability. A weighted performance counter accumulates a performance count according to a plurality of event signals provided from functional units in the processor. Differing weights are applied to the event signals in according to the correlation between each event with processor performance. The weights may be provided from programmable registers, so that the weights can be adjusted under program control. The event signals may be combined to reduce the bit-width of the set of event signal, with mutually-exclusive events merged in single fields of the combinatorial result and events having the same weights merged according to a sub-total. The weights are applied to the combinatorial result and used to update a performance count. The performance count can then be used by power management software or hardware to make adjustments in operating parameters of the processor.

Abstract: A resonant ellipsometer and method for determining ellipsometric parameters of a surface provide an efficient and low-cost mechanism for performing ellipsometric measurements. A surface of interest is included as a reflection point of a resonance optical path within a resonator. The intersection of the resonance optical path with the surface of interest is at an angle away from normal so that the complex reflectivity of the surface alters the phase of the resonance optical path. Intensity measurements of light emitted from a partially reflective surface of the resonator for orthogonal polarizations and for at least two effective cavity lengths provide complete information for computing the ellipsoidal parameters on the surface of interest. The resonator may be a Fabry-Perot resonator or a ring resonator. The wavelength of the illumination can be swept, or the cavity length mechanically or electronically altered to change the cavity length.

Abstract: A constant edge-rate ternary output consecutive-edge modulator (CEM) method and apparatus provides improved dynamic range in a noise-shaped CEM ternary pulse generator. A noise shaper shapes an input signal that is supplied to a pair of CEMs through a mismatch shaper or other code splitter that assigns unequal pulse width portions (the extra count in odd counts) between the pair of CEMs. The range of pulse width out of the CEMs can then be allowed to extend to the full sample period for one or possibly both of the CEMs in a given cycle. A control circuit overrides the mismatch shaper's assignment of the unequal pulse width portions when a previous pulse period yielded no transition from a given CEM, so that the given CEM is guaranteed to have a transition in the current pulse period.

Abstract: A cascaded pass-gate test circuit including interposed split-output drive devices provides accurate measurement of critical timing parameters of pass gates. The rise time and fall time of signals passed through the pass gate can be separately measured in a ring oscillator or one-shot delay line configuration. Inverters or other buffer circuits are provided as drive devices to couple the pass gates in cascade. The final complementary tree in each drive device is split so that the only one of the output pull-down transistor or pull-up transistor is connected to the next pass gate input, while the other transistor is connected to the output of the pass gate. The result is that the state transition associated with the device connected to the pass gate input is dominant in the delay, while the other state transition is propagated directly to the output of the pass gate, bypassing the pass gate.

Abstract: A delta-sigma having quantizer code pattern detection controlled dither reduces the probability of “stuck” code sequences that occur when the input signal and feedback signal are equal and thus no quantizer output change occurs. In particular, in modulators that are periodically reset, the pattern detection and dither control reduce the probability of a stuck code sequence at startup. A pattern detection circuit detects a sequence of unchanging quantizer output values and injects a signal at the quantizer input to cause the quantizer to change levels. The injected signal may be a dither signal that is increased in amplitude in response to the detection of unchanging code sequences and then decreased when the quantizer output changes.

Abstract: A network controller including a packet forwarding mechanism and method therefor improve load-balancing within a network system without requiring an intelligent switch having TCP splicing capability. If the network controller node is becoming overloaded (for example as indicated by a full output FIFO), the network controller forwards connections directly to alternate servers. The network controller and method further provide improved fail-safe operation, as the network controller can more easily detect failure of the coupled server than can a remote switch being monitored for failure of a connected server node. The packet forwarding mechanism can be implemented very compactly within the firmware of the network controller, providing a load-balancing solution with little incremental cost (as opposed to an intelligent switch solution) and with tight coupling to the server, providing a redirection solution from the point that has the most information available regarding the status of the associated server node.

Abstract: Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.

Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

Abstract: A delta-sigma modulator having predictive-controlled power consumption provides for reduced power consumption in analog-to-digital converters. The initial integrator stage of the delta-sigma modulator has a bias control input, which controls the level of power consumed by the integrator. The bias control input is coupled to a predictor circuit that predicts the level of change at the output of the integrator for the sample cycle. The predictor circuit may use changes in the output of the modulator quantizer alone or in combination with measured changes in the input signal in order to predict the level of change in the integrator output. The quantizer output may be differentiated to remove low frequency components and thereby provide the predictive input from the quantizer. Alternatively, steps in the quantizer output computed by differences may be used directly.

Abstract: A real-time sample rate converter having a non-polynomial convolution kernel provides reduction in die area and power for performing sample rate conversion in real-time. A non-polynomial convolution kernel, which may be a gaussian operator, is used to determine output sample values from values of an incoming stream of values. If the input sample rate is higher than the output sample rate, the input sample stream is convolved with the gaussian kernel and then decimated to yield the output stream. If the input sample rate is lower than the output sample rate, the input stream is resampled to a small multiple of the output sample rate and convolved with the gaussian kernel to produce the output sample stream directly.

Abstract: A Fabry-Perot resonator apparatus and method including an in-resonator polarizing element improves detection/measurement sensitivity of an optical system, provides both fields at a single end of the resonator, and overcomes other structural and performance limitations of particular optical systems. A polarizing element, which may be a quarter-wave plate, a 45-degree Faraday rotator or other polarizing element capable of converting between linear and circular polarizations and back, is placed in the resonance path of the Fabry-Perot resonator. The polarizing element effectively doubles the cavity length and orthogonally isolates forward from reverse reflection rays within the resonator, eliminating interference between rays and providing isolated bright and dark fields at each end of the resonator.

Abstract: A circuit and method provide rename register reallocation for simultaneous multi-threaded (SMT) processors that redistributes rename (mapped) resources between one thread during single-threaded (ST) execution and multiple threads during multi-threaded execution. The processor receives an instruction specifying a transition from a single-threaded to a multi-threaded mode or vice-versa and halts execution of all threads executing on the processor. The internal control logic then signals the resources to reallocate the resources. Rename resources are reallocated by directing an action at the rename mapper. When switching from SMT to ST mode, the mapper is directed to drop entries for the dying thread, but on a switch from ST to SMT mode, “dummy” instruction group dispatch indications are sent to the mapper that indicate use of all architected registers for each thread.

Abstract: A method and apparatus for fail-safe and restartable system clock generation provides recovery from failures due to incorrect clock generator settings or from marginal clock distribution components. Clock failure is detected at a point along the clock distribution path between the output of the clock generator and the downstream circuits. If a clock failure is detected, a second clock, which may be the clock generator reference clock, is used to operate the downstream circuits. The clock generator, which may be a phase-lock loop, is then restarted, either with a predetermined loop filter voltage at which downstream circuits are guaranteed to operate, or with a divider setting on the output of the clock generator that reduces the frequency so that downstream circuits are guaranteed to operate. Parameters of the clock generator can thereby be reset and operating conditions determined before restoring the output of the clock generator to the downstream circuits.

Abstract: A method and apparatus for determining jitter and pulse width from clock signal comparisons provides a low cost and production-integrable mechanism for measuring a clock signal with a reference clock, both of unknown frequency. The measured clock signal is sampled at transitions of a reference clock and the sampled values are collected in a histogram according to a folding of the samples around a timebase which is either swept to detect a minimum jitter for the folded data or is obtained from direct frequency analysis for the sample set. The histogram for the correct estimated period is statistically analyzed to yield the pulse width, which is the difference between the peaks of the probability density function and jitter, which corresponds to width of the density function peaks. Frequency drift is corrected by adjusting the timebase used to fold the data across the sample set.

Abstract: A dynamic logical circuit having a pre-charge element separately controlled by a voltage-asymmetric clock controlled provides increased noise immunity in dynamic digital circuits. By clocking the pre-charge element with a signal having a reduced swing in the voltage direction that turns off the pre-charge element, the pre-charge element provides a small current that prevents the dynamic summing node of a gate from erroneously evaluating due to noise, and eliminates the need for a keeper device. Providing the reduced-swing asymmetric clock as a separate signal prevents performance degradation in the rest of the circuit. Specifically, the foot devices in the dynamic portion of the circuit are controlled with the full swing clock so that evaluation is not compromised by noise or slowed. Foot and pull-up devices in any static portion of the circuit are also controlled with the full-swing clock so that switching speed and leakage immunity are not affected.

Abstract: A Fabry-Perot resonator apparatus and method for observing low reflectivity surfaces provides functional improvements for optical inspection and measurement systems, optical storage and retrieval systems as well as other optical systems when the a surface of interest in the resonator path has a lower than ideal reflectivity. The Fabry-Perot resonator is designed with an angle of incidence on the surface of interest deviating from normal incidence, effectively raising the reflectivity. Resonance is supported either by one or more reflectors oriented at angles with respect to the surface of interest, or by a focusing system that alters the directive angle of optical path(s) within the resonator such that the angle of incidence at an intersection of the optical path with the surface of interest is an angle other than normal. A normal incidence is maintained at the reflector(s), so that resonance is supported between the surface of interest and the reflector(s).

Abstract: A method and apparatus for reducing noise in a digital-to-analog converter (DAC) having a chopper amplifier output stage provides improved DAC performance. A switched-current output provided from a digital filter is coupled to the input of a chopper amplifier. The current switches are non-uniform, so that extra zeros are provided at the chopping frequency of the chopping amplifier, thereby reducing noise that would otherwise be aliased in-band at the output of the chopper amplifier. The current switches may include a first set of half-magnitude switches followed by a set of full-magnitude switches and finally by another set of half-magnitude switches having a size equal to that of the first set.