Abstract: A method of generating synthesis scripts to synthesize integrated circuit (IC) designs described in a generic netlist into a gate-level description includes the steps of identifying hardware elements in a generic netlist, determining key pins for each of the identified hardware elements, extracting design structure and hierarchy from the generic netlist, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design, and generating script to cause a logic synthesis tool to repeat these bottom-up and top-down applications until constraints are satisfied.

Abstract: A surgical portable light connector having an attachment plate so as to firmly fit onto instruments such as speculums, retractors or other instruments in the field for illumination, holding tenaculums and securing suctioning tubes and other devices. This portable attachment plate connector allows the surgeon or operators to gain the benefit of less obstructed view and conduct their procedures with more adequate space within the field of instrumentation.

Abstract: Provided are apparatuses and techniques for use by a first node on a network in determining the geographic location of a second node on the network. A data packet is received over the network from the second node, the data packet including a network identifier for the second node. Then, multiple probe packets addressed to the network identifier for the second node are sent, each of the probe packets being sent without waiting for a response from any previous probe packet.

Abstract: Methods for calculating delays for cells in ASICs are disclosed. In the present invention, delays are computed by considering not only the process (P), voltage (V), temperature (T) but also input ramptime (R) and output load or fanout (F) of the cells by fitting the delay at four corner points for derated PVT condition into a non-linear equation which is a function of P, V, T, R and F. Thus, the delay is a five dimensional characterization, and the characterization is split into (P,V,T) characterization and (R,T) characterization to reduce the characterization time and resources. The present invention provides for accurate calculation of delays for cells in ASICs.

Abstract: Combination forecasts are generated using predictions obtained from a group of forecasters. The forecasters are first divided into a number of pre-defined clusters, which typically will have been formed using statistical clustering techniques. In particular, clusters of forecasters can be formed based on similarities of the forecasters' predictions. Then, statistical data are calculated for each pre-defined cluster (e.g., measures of central tendency and dispersion). Finally, the statistical data for all the pre-defined clusters are combined so as to obtain a combination forecast.

Abstract: Video signals in different video formats are managed by inputting and outputting video signals via multiple channels and inputting a user selection of a video format for each channel. Then, a video signal input via a first channel is automatically converted into the video format selected for a second channel, and the video signal, in the video format selected for the second channel, is output via the second channel. Also, video signals in different video formats are managed by inputting and outputting video signals through multiple channels, with each such channel having an associated video format. A user designation is input that an output of a user-designated first channel should provide an output video signal corresponding to an input video signal input via a user-designated second channel.

Abstract: A database is populated with geographic locations for network devices by providing a node on a network and making a connection into a network service provider (NSP) point of presence (POP) to obtain a connection to the network via the NSP. A message is then transmitted to the node over the network connection obtained from the NSP. The message is received at the node and a source network identifier is extracted from the message. The source network identifier is then associated with a known geographic location for the POP in a database. The foregoing steps are then repeated for multiple different POPs. Also, a database is populated with geographic locations for network devices by providing a node on a network and making a connection into a network service provider (NSP) point of presence (POP) to obtain a connection to the network via the NSP. A message is then transmitted to the node over the network connection obtained from the NSP.

Abstract: Provided is a component for use in swage mounting that includes a base plate, having a first side and a second side, and a hub which preferably is cylindrically shaped. The hub is primarily comprised of a first material (such as stainless steel), extends from the second side of the base plate, and has an inner surface and an outer surface. The outer surface of the hub includes numerous protrusions that are less than approximately 50 microns in height and that are primarily comprised of a second material (such as a carbide or a nitride) which is different from the first material. Preferably, the protrusions are substantially harder (such as at least 50 hardness Vickers harder) than the base material.

Abstract: A cell for inclusion in a cell library used in designing integrated circuits. The cell includes a signal processing circuit and a buffer circuit for buffering a signal external to an integrated circuit in which the cell is to be included. The cell also includes layout information for specifying a layout of an interconnecting trace between the signal processing circuit and the buffer circuit. The invention is also directed to a method for performing layout and routing during design of an integrated circuit, in which cells are obtained from a cell library, the obtained cells are laid out on an integrated circuit die, interconnections are routed between the cells.

Abstract: A technique is described for enabling routing of metallisation wires over sensitive cells of an integrated circuit by means of a global router after the cell circuits have been designed. At least one cell includes dedicated route paths (32, 36, 40, 46) as part of the cell design. The paths may include alternative paths (32 and 36), and concurrently usable paths (40 and 46). By including the routes as part of the cell design, the subsequent problems of a global routing tool routing wires over sensitive areas of the cell can be avoided, and the number of wire routes can be controlled. The global router operates by detecting whether dedicated routes are provided and, if so, identifying the entry/exit points for routes to be used.

Abstract: Provided is an alarm for detecting radiation, smoke and/or other air pollutants and includes detection means, first means for connection to a light fitting, and second means for connection to a light source. Electrical connection means connects the first means and the second means to enable the light source to be powered from the light fitting. In addition, a battery powers the alarm during periods of non-use of the light source, and isolating means thermally isolates the detection means from at least one of the electrical connection means, the light fitting and the light source.

Abstract: When designing an electronic circuit to be implemented on an integrated circuit die which includes several metal layers, a technology-independent description of a system is generated, the technology-independent description specifying a signal and a selected metal layer for the signal. Also, an electronic circuit description of a system is synthesized from a technology-independent description of the system. Specifically, a technology-independent description of the system is input, the technology-independent description specifying a signal and a metal layer attribute for the signal. Electronic components are selected from a library based on the technology-independent description and interconnections between the electronic components are specified. A metal layer is then specified for an interconnection corresponding to the signal specified in the technology-independent description based on the metal layer attribute specified in the technology-independent description.

Abstract: The present invention includes methods for optimizing integrated circuit design by identifying a buffer tree in the integrated circuit design, the buffer tree having a plurality of vertices, each representing one of a buffer and an inverter, and also having branches, between the vertices, each representing an electrical connection. A plurality of optimization devices are applied in a random sequence to the vertices of the buffer tree. Such devices can include, for example, cell type modification; insertion of one buffer; insertion of several buffers; interchange of two grandchildren; making a grandchild into a child; making a child a grandchild; interchanging a child and a grandchild; eliminating two inverters; removing one buffer; removing more than one buffer; and removing two inverters.

Abstract: Provided is an incrementing/decrementing apparatus that includes an adder having a first input and a second input, each of the first input and the second input comprising multiple bits. A first multi-bit signal is connected to the first input, and a second multi-bit signal is connected to the second input, the second multi-bit signal including multiple bits. The adder increments the first multi-bit signal by a quantity when an increment/decrement signal has a first value and decrements the first multi-bit signal by the quantity when the increment/decrement signal has a second value. The multiple bits of the second multi-bit signal include at least one bit based solely on a corresponding bit in the quantity and at least one bit based solely on a value of the increment/decrement signal.