Abstract: The present invention discloses an apparatus for removing unwanted plants from a specific area of soil. The invention is comprised of a blade that is adapted to penetrate the surface of the soil and moving substantially parallel to the surface thereof. Proper movement of the blade is assisted by fins positioned on the sides of the blade, and act similarly to the rudder of a boat. The blade has a support member that has one end attached to the blade and the other end is capable of receiving a handle. The handle is configured in an arcuate shape to better facilitate grasping and holding by the user. This combination allows the user to grasp the handle, one hand on each side of the support member and blade, and push the invention forward undercutting the undesirable plant roots, thereby killing them. Minimal disruption of the soil is experienced, thereby optimizing the efficiency of work done by the user.

Abstract: Skew is reduced in a tree-shaped distribution network having plural levels and plural nodes at each level, where a node at one level connects to plural nodes at the next lower level. Initially, the current level is set to the bottom level of the network. Delay ranges are then obtained corresponding to nodes at the current level and the delay ranges are shifted in an attempt to align delay ranges corresponding to nodes at the current level that connect to the same node at the next higher level. These steps are then repeated for all levels in order from the bottom level to the top level.

Abstract: The invention is directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a set of areas, and a boundary pin is defined at each point on a boundary of one of the areas where the boundary of the one of the areas intersects a net. Routing optimization is then performed in at least one of the areas, the routing optimization optimizing the routing among the net pins and the boundary pins within the at least one of the areas. The invention is also directed to optimization of an initial routing that connects nets on a surface, each of the nets including plural interconnected net pins. The surface is divided into a first set of pre-defined areas, and routing optimization is performed independently in each of the pre-defined areas in the first set.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column.

Abstract: Provided is a technique for reducing skew in routing a clock signal in an integrated circuit device by prerouting an H trunk, dividing the H trunk into parts, and balancing delays in one of the parts by adding snaking wire. In a more particular aspect, the clock signal is prerouted as an H trunk, and the H trunk is divided into a left-top quadrant, a left-bottom quadrant, a right-top quadrant, and a right-bottom quadrant. The signal delays are balanced as between the two left quadrants by adding snaking wire, the signal delays are balanced between the two right quadrants by adding snaking wire, and the signal delays are balanced between the right half and the left half by adding snaking wire.

Abstract: A flip-chip integrated circuit die includes a semiconductor substrate, electronic components implemented on the semiconductor substrate, several plural metal layers, wires routed between the electronic components on the metal layers, a top layer, and bump pads arranged in a hexagonal array on the top layer. According to another aspect, the invention is directed to flip-chip integrated circuit design, in which a circuit description is input and standardized cells which correspond to electronic components in the circuit description are obtained. The standardized cells are laid out on the surface of the die using a rectangular-based layout technique, and bump pads are laid out in a hexagonal array.

Abstract: A V type nail has two side portions, at least a part of each side portion being outwardly tapered from the driven end to the leading or cutting edge thereof so as to act on woodwork or other suitable material as it is driven therein at a joint and thus obtain and maintain a tight joint.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60°. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: The application relates to a synthetic bone grafting powder mix comprising a calcium compound and protein. Preferably, the ratio by weight of the calcium compound to protein is between 90:10 to 70:30. Further, the preferred calcium compound comprises one of the following (a) Calcium Phosphate (Ca3(PO4)2); (b) Calcium Carbonate (Ca(CO3)); (c) Fluorapatite (Ca10(PO4)6F2); (d) Monetite (CaHPO4); or (e) Hydroxyapatite (Ca10(PO4)6(OH)2).

Abstract: A method of generating synthesis scripts to synthesize integrated circuit (IC) designs in RTL level description into gate-level description comprising the steps of identifying hardware elements in the RTL code, determining key pins for each of said identified hardware elements, extracting design structure and hierarchy from the RTL code, generating script to cause a logic synthesis tool to apply bottom-up synthesis to modules and sub-modules of the IC design, generating script to cause a logic synthesis tool to apply top-down characterization to modules and sub-modules of the IC design and generating script to cause a logic synthesis tool to repeat said bottom-up and said top-down applications until certain predetermined constraints are satisfied.

Abstract: A method of determining circuit characteristics of an integrated circuit design defined by RTL code, said method comprising the steps of identifying hardware elements in the RTL code, determining key pins for said identified hardware elements, and extracting critical design structure from the RTL code. The hardware elements identified include flipflops, latches, tristate buffers, bidirectional buffers and memories. The critical design structures include design hierarchy and nets, including clock nets, multiply-driven nets, reset nets, and RAM write enable nets.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. In order to design circuits to meet a given set of requirements, each signal path of the circuit must be analyzed. Because of the large number of the cells and the complex connections, the number of paths is very large and requires much computing power to analyze. Also, some of the paths are not important for the purposes of the operations of the chip and can be discounted during the analysis process. The present invention discloses a method and apparatus used to avoid analyzing non-important paths, referred to as false paths of a directed timing graph.

Abstract: A method for routing nets in an integrated circuit design, said method comprising the steps of forming a routing graph for an integrated circuit design, said routing graph have edges in a first direction and edges in a second direction, globally routing said integrated circuit design in accordance with said routing graph, dividing the routing graph into strips, for each strip in the routing graph, generating a general task for optimizing the routing in the strip, solving general tasks in parallel by assigning different processors different strips to process.

Abstract: A method of determining circuit characteristics of an integrated circuit design as defined by a generic netlist comprising the steps of identifying hardware elements in the generic netlist, determining key characteristics for each of said identified hardware elements, determining interconnections of said identified hardware elements, and detecting the degree of conformity of said identified hardware elements, said key characteristics, and said interconnections to predetermined configurations. The systems further identifies all cells in the generic netlist, determines for each cell the type of cell, accumulates cell types and cell type counts, and notifies an operator of said accumulated values.

Abstract: Provided is an apparatus directed to identifying desired combinations of musical notes. The apparatus includes a base imprinted with plural different indicia, each different indicium corresponding to a different musical note. For example, the indicia might include musical symbols (e.g., C or G♯/A♭) and/or might include a different color or combination of colors for each note. A template having plural windows may be disposed over the base so as to selectively view plural of the different indicia. It is a feature of the invention that the template corresponds to a particular characteristic, such as the major scales or the minor ninth chords, and different positions of the template relative to the base reveal different sets of musical notes having said characteristic. For example, one position of the template might reveal the C major scale and another might reveal the A♯/B♭ major scale.

Abstract: A method of fabricating an integrated circuit chip (IC), said method comprising the steps of defining the IC at the RTL code level, translating said RTL code into a generic netlist description, generating logic synthesis tool scripts based on said generic netlist description, and executing said logic synthesis tool scripts to synthesize the RTL code. The step of generating logic synthesis tool scripts comprises the substeps of identifying hardware elements and structure of the IC design, determining interrelationships between said identified hardware elements and structures, and generating logic synthesis tool scripts to synthesize said identified hardware elements to netlists as a function of said hardware elements and said interrelationships.