Patents Represented by Attorney Mitchell, Silberberg & Knupp
  • Patent number: 6681373
    Abstract: The present invention includes methods for optimizing integrated circuit design by identifying a buffer tree in the integrated circuit design, the buffer tree having a plurality of vertices, each representing one of a buffer and an inverter, and also having branches, between the vertices, each representing an electrical connection. A plurality of optimization devices are applied in a random sequence to the vertices of the buffer tree. Such devices can include, for example, cell type modification; insertion of one buffer; insertion of several buffers; interchange of two grandchildren; making a grandchild into a child; making a child a grandchild; interchanging a child and a grandchild; eliminating two inverters; removing one buffer; removing more than one buffer; and removing two inverters.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: January 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Andrej A. Zolotykh, Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev
  • Patent number: 6678711
    Abstract: Provided is an incrementing/decrementing apparatus that includes an adder having a first input and a second input, each of the first input and the second input comprising multiple bits. A first multi-bit signal is connected to the first input, and a second multi-bit signal is connected to the second input, the second multi-bit signal including multiple bits. The adder increments the first multi-bit signal by a quantity when an increment/decrement signal has a first value and decrements the first multi-bit signal by the quantity when the increment/decrement signal has a second value. The multiple bits of the second multi-bit signal include at least one bit based solely on a corresponding bit in the quantity and at least one bit based solely on a value of the increment/decrement signal.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: January 13, 2004
    Assignee: LSI Logic Corporation
    Inventor: Subba Rao Kalari
  • Patent number: 6674166
    Abstract: Tile-based routing between a bump pad and an input/output (I/O) device for implementation on a flip-chip integrated circuit (IC) die. A trace is routed between the bump pad and a position corresponding to a first I/O slot, the first I/O slot being at least partially occupied by the I/O device. A position is obtained for a device pad for the I/O device. The trace is then extended into an area corresponding to the position obtained for the device pad. It is a feature of this aspect of the invention that the trace extension extends the trace into a pad area for a second I/O slot, the second I/O slot being at least partially occupied by the I/O device. The invention also concerns a flip-chip integrated circuit (IC) die that includes a bump pad, an input/output (I/O) device, and a device pad electrically connected to the I/O device and disposed vertically adjacent to a portion of the I/O device.
    Type: Grant
    Filed: January 19, 2001
    Date of Patent: January 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Ramoji Karumuri Rao, Mike Liang
  • Patent number: 6658467
    Abstract: Resources are provided to participants over an electronic network by maintaining a collection of resources that can be accessed by a participant over the electronic network at a given time. Points are assigned to each resource based on participant access of the resource and the collection is modified based on the points assigned to each resource. Alternatively, or in addition, participants may be permitted to rate the resources, with points assigned to each resource based on participant rating of the resource. The collection of resources is then modified based on assigned points for each resource.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: December 2, 2003
    Assignee: C4cast.com, Inc.
    Inventors: Mark E. Rice, Stephen A. Klein, G. Michael Phillips, M. Chapman Findlay, III, William P. Jennings
  • Patent number: 6637011
    Abstract: The present invention is a method for searching an identity base for identities that can be applied to a given formula. The method includes transforming the formulas from an identity base into a standard form, creating a set of code words for said identity base, constructing a lexicographical tree of a code word set of said identity base, and outputting a list of formula numbers from said identity base.
    Type: Grant
    Filed: October 2, 2000
    Date of Patent: October 21, 2003
    Assignee: LSI Logic Corporation
    Inventors: Andrej A. Zolotykh, Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev
  • Patent number: 6636552
    Abstract: Provided is a method and an apparatus for pseudo-random noise (PN) code sequence hopping, in which an output PN code sequence is generated by generating and combining several intermediate PN code sequences, each of the intermediate PN code sequences being generated by a corresponding PN code sequence generator. A base state is stored for each of the plural intermediate PN code sequences, and the number of states to advance the output PN code sequence is identified, the number being greater than one. A transformation function is obtained for each of the plural intermediate PN code sequences, based on the number of states to advance the output PN code sequence, and then the base state for each intermediate PN code sequence is advanced by the number of states to advance the output PN code sequence, by utilizing the transformation function for such intermediate PN code sequence, to obtain a new state for such intermediate PN code sequence.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: October 21, 2003
    Assignee: LSI Logic Corporation
    Inventor: Brian C. Banister
  • Patent number: 6634014
    Abstract: Delay and/or load estimation is performed prior to physical layout in an integrated circuit (IC) design process. Initially, a description of the IC design is obtained, the description being in a hardware description language (HDL). Floor planning is then performed based on the HDL description, and buffers are inserted into the IC design based on such floor planning. Finally, delays and/or loads are estimated in the IC design while taking into account the effect of the buffers. The buffers are inserted in the foregoing processing based on anticipated processing later in the IC design process.
    Type: Grant
    Filed: December 12, 2000
    Date of Patent: October 14, 2003
    Assignee: LSI Logic Corporation
    Inventors: Grant Lindberg, Stefan Graef
  • Patent number: 6624611
    Abstract: Provided is an apparatus that includes temperature-sensitive functional means for performing pre-configured functionality (such as video recording), mounting means for mounting the apparatus to a motor vehicle, and heating means for heating the functional means. Detection means detects at least one of: whether an automobile battery in the automobile is being charged and whether an engine block in the automobile is being heated. Control means controls the heating means and initiates a heating process upon detection by the detection means.
    Type: Grant
    Filed: August 9, 2002
    Date of Patent: September 23, 2003
    Assignee: Taw Security Concepts, Inc.
    Inventor: Charles Bruno Kirmuss
  • Patent number: 6616702
    Abstract: A system which enables a user to preview a document by providing a user interface and inputting, via the user interface, information specifying an arrangement of components to create the document, the components including at least two of: a printed page, a tab page, a blank page, a front cover, a back cover, and a binding. Digital images of at least some of the components specified by the input information are obtained and an image of the document is generated by combining the digital images of at least some of the components in a manner so as to simulate an appearance of the document were the document to be physically assembled according to the input information. The image of the document is then caused to be displayed. Also, a system which enables a user to preview a document by providing a user interface and inputting information, via the user interface, (1) specifying a source file which contains content for the document, (2) specifying an arrangement of components to create the document, the.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 9, 2003
    Assignee: Kinko's Ventures, Inc.
    Inventor: Robert Tonkin
  • Patent number: 6612430
    Abstract: Provided is a display panel for displaying and/or storing shoes. The display panel includes a base board defined by a first side, a second side and a peripheral edge. The base board has a first cut in a shape of a sole of a left shoe and a second cut in a shape of a sole of a right shoe. An upper portion of a left shoe is attached to an area of the second side that is enclosed by the first cut, and an upper portion of a right shoe is attached to an area of the second side that is enclosed by the second cut.
    Type: Grant
    Filed: November 24, 2000
    Date of Patent: September 2, 2003
    Assignee: Seychelles Imports LLC
    Inventor: Albert J. Silvera
  • Patent number: 6606342
    Abstract: Provided is a method and apparatus for pseudo-random noise (PN) code sequence hopping by storing a base state of a PN code sequence generator that generates a PN code sequence and by identifying a number of states to advance the PN code sequence, the number being greater than one. A transformation function is then obtained based on the number of states to advance the PN code sequence. The PN code sequence is advanced by the identified number of states from the base state to obtain a new state, by utilizing the transformation function. Finally, the new state is loaded into the PN code sequence generator and the PN code sequence generator is enabled with the new state.
    Type: Grant
    Filed: November 16, 1999
    Date of Patent: August 12, 2003
    Assignee: LSI Logic Corporation
    Inventor: Brian C. Banister
  • Patent number: 6606615
    Abstract: Provided is a contest that produces forecasting data for predesignated variables whose values change over time. Initially, participant registrations are accepted, and the participants are permitted to submit predictions of values, projected at plural different time points, for at least one of several predesignated variables. Then, the participants receive an overall ranking based on their relative accuracies (e.g., percentile rankings) in individual prediction events. Additional features of the invention include: requiring demographic information as a condition to registration, rewarding participants for updating their predictions as early as possible, basing overall ranking on both accuracy and accuracy consistency in individual prediction events, basing the overall ranking on how soon the participants' final predictions were made before certain closing time points, and permitting participants to submit estimates of their own prediction uncertainty.
    Type: Grant
    Filed: September 8, 1999
    Date of Patent: August 12, 2003
    Assignee: C4Cast.com, Inc.
    Inventors: William P. Jennings, M. Chapman Findlay, III, G. Michael Phillips, Stephen A. Klein, Mark E. Rice
  • Patent number: 6590289
    Abstract: Cell terminals in an integrated circuit is interconnected by using multiple layers of conductors that are routed both orthogonally and non-orthogonally to each other. Non-orthogonally routed conductors have slopes that are ratios of non-zero integers which approximate ceratin predetermined angles. The integers in the ratios are chosen from integers generated by sequence equations. The conductors are routed by following grid lines in a grid system comprising both orthogonal grid lines and non-orthogonal grid lines having slopes generated by the sequence equations. Ratios of integers are used to approximate certain angles so that the conductors would intersect the cell terminals located on the fundamental grid intersection points. The conductors in different metal layers form different angles with other conductors in other metal layers based on the slopes of the conductors.
    Type: Grant
    Filed: May 17, 2001
    Date of Patent: July 8, 2003
    Assignee: LSI Logic Corporation
    Inventor: John Shively
  • Patent number: D481750
    Type: Grant
    Filed: October 18, 2002
    Date of Patent: November 4, 2003
    Assignee: Fitovers Eyewear Ltd. Pty.
    Inventor: Paul J. Stables
  • Patent number: D481751
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: November 4, 2003
    Assignee: Fitovers Eyewear Ltd. Pty.
    Inventor: Paul J. Stables
  • Patent number: D482471
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: November 18, 2003
    Assignee: Gold Coral International Limited
    Inventor: Stephanie Wai Man Shiu
  • Patent number: D482472
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: November 18, 2003
    Assignee: Gold Coral International Limited
    Inventor: Stephanie Wai Man Shiu
  • Patent number: D482473
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: November 18, 2003
    Assignee: Gold Coral International Limited
    Inventor: Stephanie Wai Man Shiu
  • Patent number: D484624
    Type: Grant
    Filed: January 7, 2003
    Date of Patent: December 30, 2003
    Assignee: Gold Coral International, Ltd.
    Inventor: Stephanie Wai Man Shiu
  • Patent number: D485058
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: January 13, 2004
    Assignee: Gold Coral International Limited
    Inventor: Stephanie Wai Man Shiu