Abstract: The present invention is a method and apparatus for optimizing the design of a combinational circuit. The method includes constructing a circuit sheaf for the combinational circuit and then performing vector optimization with domination. In the preferred embodiment, a complete BDD B is determined and, from that, a list of F-sets is computed. If the combinational circuit includes cells other than NOT, AND and XOR cells, the circuit is first transformed such that it only has those types of cells.

Abstract: Provided are systems and methods for facilitating loading of data from a portable medium into a device. Initially, a portable medium encoded with data is accepted and the data from the portable medium is loaded into a mass storage device. A paging signal is caused to be wirelessly transmitted when a specified portion of such loading has been completed.

Abstract: An improved device or tool is provided for cleaving angled ends on to at least one optical fiber (1) (FIG. 1) in which spring means (6) and co-operating pivotally mounted clamping blocks (7a, 7b) are employed to clamp and tension the optical fiber (1) with tension (T). A sharp corner edge (11) of an anvil (10) is used to locally deflect or displace the fiber (1) and bend it about the opposing sharp corner edge (12) of the clamping surface (5) of one of the clamping blocks (viz 7b) so that the fiber experiences a localized shear force. The resultant stress is a superposition of tension and shear and is directed away from the axis of the fiber (1). An acutely angled blade (13) is operable to score the fiber (1) at a point between the two opposing corners (11, 12). The fiber (1) cleaves with ends which are consistently angled at between 1° and 20° (preferably 5° to 10°) away from the perpendicular to the fiber axis.

Abstract: A message that has its energy spread over a frame of encoded data is decoded. First, encoded data are received so as to obtain a quantity of the encoded data that is less than all the encoded data in the frame and also is less than all the encoded data representing the message. Then, the quantity of encoded data received is supplemented, without receiving additional encoded data, so as to obtain a frame of data. Typically, the data will be supplemented by zero padding the data, such as by initializing a frame buffer to all zeros and then overwriting the zero data with actual data as it is received. Finally, ordinary frame decoding is performed on the frame of data so generated, in order to decode the message.

Abstract: The present invention comprises method for optimizing an integrated circuit design that includes computing of capacities and delays of an integrated circuit design, resynthesizing said integrated circuit design utilizing a plurality of local optimization procedures, and removing overlap the local optimization procedures can include a local resynthesis of logic trees procedure that utilizes multiple cost functions, a dynamic buffer and inverter tree optimization procedure, and a cell resizing procedure. Generally, faster local optimization procedures are applied first and slower, more thorough procedures are applied to areas where the faster procedures have not solved the optimization tasks.

Abstract: A modeling apparatus for producing a model by lamination of sheet material including a support platform which can be raised and lowered, a sheet feed mechanism for feeding sheet material over the platform, a superstructure mounted over the platform, a cutting mechanism for cutting the sheet material to form shaped portions, an adhesive applicator for applying adhesive to the shaped portions, and a control mechanism.

Abstract: Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.

Abstract: Methods for calculating a total capacitance of a metal wire in an integrated circuit is disclosed. In the present invention, a library containing predetermined wiring topologies is created. Each of the wiring topologies has an associated capacitive value. After extracting a layout topology of a segment of the metal wire, the layout topology is used to find and extract one of the predetermined wiring topologies in the library that corresponds to the layout topology. The associated capacitive value for the extracted wiring topology is used to calculate the total capacitance of the metal wire.

Abstract: Provided is an analog-to-digital converter that includes a first analog-to-digital conversion (ADC) stage connected to input a first analog signal and a second ADC stage connected to input a second analog signal produced by the first ADC stage. A tone detector enables the second ADC stage from a disabled state when a first condition indicating the presence of a high-level interference tone is satisfied and disables the second ADC stage from an enabled state when a second condition indicating the absence of a high-level interference tone is satisfied.

Abstract: Constant pins are determined in a combinational circuit by associating an input of a combinational circuit with a first variable and a second variable, with the second variable being the complement of the first variable. For a first logical cell interconnected to such input, a first mathematical representation and a second mathematical representation are computed. The first mathematical representation is a function of the operation of the first logical cell and a function of the first variable, and the second mathematical representation is a function of the operation of the first logical cell and a function of the second variable. A determination is then made as to whether one of the first and second mathematical representations is equal to a constant.

Abstract: The present invention selects parts of an integrated circuit description for resynthesis and then prepares those parts for resynthesis. Initially, a resynthesis goal is input, with the resynthesis goal having been selected from a set of possible resynthesis goals. Plural buffer and/or logic trees in the integrated circuit description are then selected based on the resynthesis goal, and information for each of the selected trees is obtained and stored. The tree information includes: (i) a description of each tree cell, including cell types, cell coordinates, and flips and angles of the tree cell, (ii) a description of each input net, (iii) a signal arrival time for each input net as a function of a capacity of such input net, (iv) coordinates of each pin driving each input net, and (v) a maximum capacity of each input net that will prevent such input net from having a timing violation.

Abstract: The present invention involves a method for determining constant pins in a combinational circuit. The method comprises the steps of associating an input of a combinational circuit with a first variable and a second variable, wherein said second variable is the compliment of said first variable, computing for a first logical cell interconnected to said input a first canonical representation, wherein said first canonical representation is a function of the operation of said first logical cell and a function of said first value, computing for said first logical cell a second canonical representation, wherein said second canonical representation is a function of the operation of said first logical cell and a function of said second value, determining whether one of said first and second canonical representations is equal to zero.

Abstract: The present invention involves a method for reducing delay of a net. The method includes constructing a time-space grid, said time-space grid corresponding to a net, passing a wave through the time-space grid, said wave having a wave value, and inserting a buffer at a point on said time-space grid where insertion of the buffer increases a wave value. The buffer can be a negative buffer or positive buffer. Generally, a second wave is passed through the time-space grid simultaneously with the first wave. Typically, the second wave and the first wave are inverted.

Abstract: The present invention is a method and apparatus for applying proximity correction to a piece of a mask pattern, by segmenting the piece into a plurality of segments, and applying proximity correction to a first segment without taking into consideration the other segments of the piece.

Abstract: Methods for calculating delays for cells in ASICs are disclosed. In the present invention, delays are computed by considering not only the process (P), voltage (V), temperature (T) but also input ramptime (R) and output load or fanout (F) of the cells by fitting the delay at four corner points for derated PVT condition into a non-linear equation which is a function of P, V, T, R and F. Thus, the delay is a five dimensional characterization, and the characterization is split into (P,V,T) characterization and (R,T) characterization to reduce the characterization time and resources. The present invention provides for accurate calculation of delays for cells in ASICs.

Abstract: Provided is a technique for designing an integrated circuit die which includes a semiconductor layer, a primary metal layer, a horizontal metal layer and a vertical metal layer. Electronic components are laid out on the semiconductor layer, and a primary power distribution network for distributing power to the electronic components is laid out on the primary metal layer. Then, a uniform trunk width is calculated for all trunks in a power mesh based on a desired maximum voltage drop for the generated electronic component layout. Finally, horizontal power trunks are laid out on the horizontal metal layer and vertical power trunks are laid out on the vertical metal layer using the calculated uniform trunk width, so as to form the power mesh, and an electrical connection is specified between the power mesh and the primary power distribution network.

Abstract: The present invention is directed to laying out connection points and routing a signal from an input terminal to the connection points for use in signal distribution to control skew. A pattern of diamond-shaped rings is constructed, each of the diamond-shaped rings including an inner diamond, an outer diamond and all space between the inner diamond and the outer diamond, where the diamond-shaped rings are arranged such that each point within a specified area is included within at least one diamond-shaped ring. A center point is identified for each of the diamond-shaped rings and each center point is designated as a connection point. A connection is then routed between the input terminal and each of plural of the connection points. The invention also is directed to routing a signal from one of plural connection points to a pin so as to control skew.