Abstract: A fin field effect transistor (fin FET) is formed using a bulk silicon substrate and sufficiently guarantees a top channel length formed under a gate, by forming a recess having a predetermined depth in a fin active region and then by forming the gate in an upper part of the recess. A device isolation film is formed to define a non-active region and a fin active region in a predetermined region of the substrate. In a portion of the device isolation film a first recess is formed, and in a portion of the fin active region a second recess having a depth shallower than the first recess is formed. A gate insulation layer is formed within the second recess, and a gate is formed in an upper part of the second recess. A source/drain region is formed in the fin active region of both sides of a gate electrode.

Abstract: In one embodiment, a non-volatile memory device includes an isolation film defining an active region in a semiconductor substrate; a tunnel insulating film located on the active region; a control gate located on the isolation film; an inter-gate dielectric film parallel to the control gate and located between the control gate and the isolation film; an electrode overlapped by the control gate and the inter-gate dielectric film, wherein the electrode extends over the tunnel insulating film on the active region to form a floating gate; and a source region and a drain region formed in the active region on both sides of the floating gate.

Abstract: A method of precisely inspecting the entire surface of a mask at a high speed in consideration of optical effects of the mask. The method includes designing a target mask layout for a pattern to be formed on a wafer, and extracting an effective mask layout using an inspection image measured from the target mask layout using an aerial image inspection apparatus as a mask inspection apparatus. The effective mask layout is input to a wafer simulation tool for calculating a wafer image to be formed on the wafer. Optical effects of the mask are detected by comparing the target mask layout with the effective mask layout.

Abstract: Provided are a stack package and a stack packaging method. The stack package includes: a first package; and a second package stacked on the first package, wherein external leads of the first package and the second package are directly connected to one another and inner leads thereof are arranged in different shapes so that the Chip Select signal of the second package are input through a No Select pin of the first package.

Abstract: An image sensor package assembling method includes providing a substrate on which a plurality of image sensors are mounted; providing a housing strip having a plurality of housings arranged corresponding to an arrangement of the image sensors on the substrate, each of the housings having an aperture corresponding to an active surface of the corresponding image sensor and a cavity enclosing an edge of the corresponding image sensor; attaching a transparent cover plate sealing the apertures of the housings on the housing strip after attaching the housing strip on the substrate; and separating image sensor packages from each other by successively cutting the transparent cover, the housing strip and the substrate. Increased yield and production efficiency can be realized.

Abstract: A method of programming a nonvolatile memory device. The method may include pre-programming one memory cell among a plurality of memory cells by storing data in a first data storage layer using a first program voltage applied to one word line corresponding to the one memory cell among the plurality of memory cells; and while pre-programming other memory cells among the plurality of memory cells, background-programming the pre-programmed memory cell by moving the stored data to a second data storage layer using a second program voltage that is higher than the first program voltage applied to the word line of the pre-programmed memory cell.

Abstract: A semiconductor memory device includes a plurality of memory cell array blocks, a bit line sense amplifier, a local sense amplifier that can be controlled to be turned on or off, a data sense amplifier, and a controller. The controller activates a local sense control signal for a predetermined duration in response to first and second signals. The first signal is a bit line sense enable signal that activates the bit line sense amplifier, and the local sense amplifier is activated for a predetermined duration after the bit line sense enable signal is activated. The second signal is activated or deactivated in phase with a column selection line signal that connects a pair of bit lines and a pair of local input/output lines. Accordingly, it is possible to turn on or off the local sense amplifier according to operating conditions, thereby increasing a tRCD parameter and reducing the consumption of current.

Abstract: Provided are a tape substrate for a smart card, a method of fabricating the same, and a semiconductor module and a smart card using the tape substrate. The tape substrate includes at least one tape unit. The at least one tape unit includes a chip mounting unit defining a region on which a semiconductor chip is to be mounted, a plurality of pin electrode units arranged around the chip mounting unit and separated from one another, a border unit encircling the chip mounting unit and the pin electrode units, and a cutting unit disposed between the chip mounting unit and the border unit and between the pin electrode units and the border unit. The cutting unit includes a plurality of connection lines connecting the chip mounting unit and the pin electrode units to the border unit.

Abstract: Provided are a semiconductor device and a method of fabricating the same, and more particularly, a semiconductor package and a method of fabricating the semiconductor package. The semiconductor package includes a first package that comprises a first substrate, at least one first semiconductor chip stacked on the first substrate, and first conductive pads exposed on a top surface of the first substrate; a second package disposed below the first package such that the second package comprises a second substrate, at least one second semiconductor chip, and second conductive pads exposed on a bottom surface of the second substrate; and a connection unit that extends from the first conductive pads to the second conductive pads such that the connection unit covers a side surface of the first package and a side surface of the second package in order to electrically connect the first package to the second package.

Abstract: A stack package of the present invention is made by stacking at least two area array type chip scale packages. Each chip scale package of an adjacent pair of chip scale packages is attached to the other in a manner that the ball land pads of the upper stacked chip scale package face in the opposite direction to those of the lower stacked chip scale package, and the circuit patterns of the upper stacked chip scale package are electrically connected to the those of the lower stacked chip scale package by, for example, connecting boards. Therefore, it is possible to stack not only fan-out type chip scale packages, but to also efficiently stack ordinary area array type chip scale packages.

Abstract: A method of analyzing ions adsorbed on a surface of a mask for pattern formation of a semiconductor device, and an apparatus using the same are disclosed. The ion analyzing method includes: filling a heating container within a main chamber with a predetermined amount of a solvent; immersing a mask in the solvent-filled heating container; raising an internal pressure of the chamber to a predetermined level by supplying gas into the chamber; separating ions from a surface of the mask by heating the solvent within the heating container at a predetermined temperature for a predetermined period; and analyzing the ions by collecting the solvent.

Abstract: A flash memory device which comprises a memory cell array having memory cells arranged in rows and columns; a word line voltage generator circuit configured to generate a program voltage, a dielectric breakdown prevention voltage, and a pass voltage at a program operation; and a row selector circuit that receives the program voltage, the dielectric breakdown prevention voltage, and the pass voltage and selecting one of the rows in response to a row address. The dielectric breakdown prevention voltage is lower than the program voltage and higher than the pass voltage; and the row selector circuit drives the selected row with the program voltage, drives at least one row just adjacent to, or neighboring, the selected row with the dielectric breakdown prevention voltage and drives remaining rows with the pass voltage.

Abstract: A non-volatile semiconductor memory device includes: cell strings connected to respective bit lines; each of the cell strings having a string select transistor connected to a string select line, a ground select transistor connected to a ground select line, and memory cells connected to corresponding word lines and connected in series between the string select transistor and the ground select transistor; a first voltage drop circuit configured to reduce an applied read voltage during a read operation; a second voltage drop circuit configured to reduce the applied read voltage; a string select line driver circuit configured to drive the string select line with the reduced voltage provided by the first voltage drop circuit; and a ground select line driver circuit configured to drive a ground select line with the reduced voltage provided by the second voltage drop circuit.

Abstract: Embodiments of methods, transceiver circuits, and systems can compensate an IQ mismatch (e.g., Tx or Rx) or a carrier leakage using a plurality of local oscillators. One embodiment of a transceiver can include a first up-conversion IQ mixer, a second up-conversion IQ mixer, a first down-conversion IQ mixer with an input to receive an output of the second up-conversion IQ mixer, a second down-conversion IQ mixer with an input to receive an output of the first up-conversion IQ mixer, a first local oscillator to generate a first IQ LO signal for the first up-conversion IQ mixer and the first down-conversion IQ mixer, and a second local oscillator to generate a second IQ LO signal for the second up-conversion IQ mixer and the second down-conversion IQ mixer.

Abstract: Provided are a wafer level chip scale package in which a redistribution process is applied at a wafer level, a manufacturing method thereof, and a semiconductor chip module including the wafer level chip scale package. The wafer level chip scale package includes a semiconductor chip having a bonding pad, a first insulating layer disposed on the semiconductor chip so as to expose the bonding pad, a redistribution line disposed on the exposed bonding pad and the first insulating layer, a sacrificial layer disposed below a redistribution pad of the redistribution line, a second insulating layer disposed on the redistribution line so as to expose the redistribution pad and including a crack inducement hole disposed beside the sacrificial layer, and an external connection terminal attached to the redistribution pad.

Abstract: A field-effect transistor including localized halo ion regions that can optimize HEIP characteristics and GIDL characteristics. The field-effect transistor includes a substrate, an active region, a gate structure, and halo ion regions. The active region includes source/drain regions and a channel region formed at a partial region in the substrate. The gate structure electrically contacts the active region. The halo ion regions are locally formed adjacent to both end portions of the source/drain regions in the substrate.

Abstract: A highly reliable semiconductor device and a method fabricating the same are provided, the semiconductor device having a low resistance electrode structure. The semiconductor device includes an interlayer insulation film formed on a semiconductor substrate. A storage node electrode is formed on the interlayer insulation film. A protection film is formed on the storage node electrode and includes a nitrided metal film. A dielectric film overlies the protection film. A plate electrode is formed on the dielectric film.

Abstract: A phase change memory device includes wordlines extending along a direction on a semiconductor substrate. Low concentration semiconductor patterns are disposed on the wordlines. Node electrodes are disposed on the low concentration semiconductor patterns. Schottky diodes are disposed between the low concentration semiconductor patterns and the node electrodes. Phase change resistors are disposed on the node electrodes.

Abstract: An On Die Termination (ODT) circuit for performing an ODT operation. The ODT circuit includes a resistor having a first end to receive an ODT enable signal; and a switch unit coupled to a second end of the resistor. The ODT operation is performed in response to the ODT enable signal passing through the resistor.

Abstract: The apparatus for transferring the semiconductor chip includes: a holder member including a first vacuum hole connected to a vacuum line; a plate member including at least one second vacuum hole corresponding to the first vacuum hole and redistributed to edges of the plate member, the plate member combined with the holder member; and an absorption member including at least one third vacuum hole corresponding to the second vacuum hole and a groove connected to the third vacuum hole, the absorption member combined with the plate member and the holder member.