Abstract: A method and apparatus for indicating information to a user of a palmtop computer. Illuminatable hard buttons are disclosed that are operable for performing functions. The hard buttons are selectively illuminated to indicate information to a user that relates to the function performed when the bard button is pressed. The selective illumination of hard buttons to indicate information that relates to the function that is performed when the hard button is pressed conveys information to the user in a manner that is easily understood by the user. In one embodiment, whether or not the button is illuminated and the color of the illumination, convey information about the function that is to be performed when the button is pressed.

Abstract: Embodiments of the present invention provide a striped or closed cell trench metal-oxide-semiconductor field effect transistor (TMOSFET). The striped or closed cell TMOSFET comprises a source region, a body region disposed above the source region, a drift region disposed above the body region, a drain region disposed above the drift region. A gate region is disposed above the source region and adjacent the body region. A gate insulator region electrically isolates the gate region from the source region, body region, drift region and drain region. The body region is electrically coupled to the source region.

Abstract: A method and circuit thereof for performing setup and hold (SUAH) testing on integrated circuits including, but not limited to SRAM, utilizing a relatively low number of test vectors, obviating the conventional requirement of writing to and reading back from each and every memory address. In one embodiment, a first test data signal of all zeros (0) is inputted to the input stage of the SRAM under test, and a subsequent second data signal of all ones (1) follows. In one embodiment, XOR/XNOR gates detect differences in data signals between the inputs and outputs of input stage latches/registers after clocking. In one embodiment, detected differences are combined into an error signal in combinational logic. In one embodiment, error signals are exported serially to a test system by a scan chain. Alternatively, in another embodiment, error signals are exported in parallel via individual output drivers.

Abstract: A method and system for automatically building a bit order data structure of configuration bits for a programmable logic device. One embodiment of the present invention first identifies a plurality of memory cells in a hierarchical schematic representation of the programmable device. Next, this embodiment determines a plurality of addresses corresponding to the plurality of memory cells. This embodiment next determines a plurality of logical names for the plurality of memory cells. Then, based on an order in which the plurality of addresses are to be loaded into the programmable logic device, this embodiment orders the plurality of logical names for the plurality of memory cells. Another embodiment first accesses a database comprising a plurality of logical names corresponding to a plurality of addresses. Then, this embodiment accesses a database specifying an order in which the plurality of addresses are to be loaded into the programmable logic device.

Abstract: A method and system for controlling the processing of an IC chip assembly line using a central computer system and a common communication protocol. In one embodiment, a manufacturing execution system (MEM) is used as the computer system and the communications protocol is the standard semi equipment communications standard/generic equipment model (SECS/GEM). One or more equipment cell controllers (CC) may be used to communicate between the MES a plurality of in-line substations which comprise the assembly line. Automated vision camera systems may also communicate information to the MES via the CCs. In one embodiment, the MES maintains a database in memory comprising processing history of a die-strip and results of automated die-strip examination from the vision camera systems. In one embodiment, the die-strip may be of a ball grid array (BGA) type.

Abstract: Embodiments of the present invention provide a method of centering an operating band of a voltage controlled oscillator around a desired operating frequency. In one embodiment, an adjustable feedback divider provides for driving an output signal to the top and bottom of the operating band. An adjustable period divider and counter provide a plurality of count values for use in determining a mid-point of the operating band. A capacitance bank provides for selectively adjusting a capacitance of the voltage controlled oscillator, thereby adjusting the operating band.

Abstract: A device aging determination circuit. Circuits are located on a device, including a first circuit operating at a first duty cycle and generating a first output and a second circuit operating at a second duty cycle different from said first duty cycle and generating a second output. A measuring circuit determines a difference in the first output and the second output, wherein the difference indicates an aging of the device. The aging is a representation of how much degradation the device has been exposed to, and allows for dynamic adjustment of operating parameters of the device to optimize performance.

Abstract: A method and system for performing chaincast communication to multiple communication systems (e.g., computer systems) within a system of coupled electronic devices (e.g., the Internet). The present invention provides a system wherein a broadcast source communicates primary broadcast information (e.g., encoded audio radio content, encoded audio/video television content, etc.) to a first group of electronic devices. The first group of electronic devices can be instructed by a chaincast manager to then communicate (e.g., forward or retransmit) the broadcast information to other electronic devices which devices can also be instructed to communicate to more devices, etc., thereby reducing the bandwidth requirements of the communication channel between the broadcast source and the first group of electronic devices. The chaincast manager, coupled to the Internet, is used to track and manage which devices are forwarding broadcast information to which other devices.

Abstract: A method for fabricating a junction field transistor for high-voltage applications. A lightly doped first epitaxial layer is formed on a highly doped substrate. A second epitaxial layer is deposited with a heavier dopant concentration than the first epitaxial layer. The second layer contains a control structure having a plurality of implanted gate regions and a source. A guard ring is formed to isolate the source and the control structure. The combination of the lightly doped first epitaxial layer and the guard ring enable the JFET to be operated with a breakdown voltage in excess of 100 volts. Multiple guard rings may be used to provide a breakdown voltage in excess of 150 volts.

Abstract: Embodiments of the present invention relate to a low voltage differential signal driver (LVDS) circuit which comprises a current source, logic controlled switches for controlling the driver's output, an electronic load circuit coupled across the circuit, and a common-mode resistor feedback circuit coupled across the circuit, in parallel with the RC load, for tuning the driver's impedance. The driver is enabled to operate without op-amps and achieves optimum performance at 1.8 v supply voltages.

Abstract: A digitally controlled hybrid power module is controlled by a programmable controller. The hybrid power module includes a digitally controlled switching supply with an output coupled to an input of a digitally controlled linear voltage regulator. Independent control of switching supply and the linear regulator is provided by the programmable controller, which may be a field programmable gate array (FPGA), microcontroller, or digital signal processor (DSP). The programmable controller may independently control one or more power modules. Each power module may also include enable switching and an associated current clamp for capacitive loads. An output voltage transient suppressor may also be used to control transients, such as those produced under fast switching conditions.

Abstract: A system and method for graphically displaying global resources and their associated parameter values and apply the global resources across multiple design projects. The system and method also provide a graphical interface which displays the possible parameter values of an associated global resource. This graphical interface utilizes pop up menu to for viewing the possible parameter values and the selection of the current parameter value. The system and method also provide tracking and updating of the hardware resources which utilize the parameter values of the global resources. Further, the system also allows the storage of these parameters values of the global resources. By storing these parameter values of the global resources, these parameter values can be set as default global settings. These default global settings can be recalled and associated with different projects without manual entry of the parameter values.

Abstract: Systems and methods for reducing temperature dissipation during burn-in testing are described. Devices under test are each subject to a body bias voltage. The body bias voltage can be used to control junction temperature (e.g., temperature measured at the device under test). The body bias voltage applied to each device under test can be adjusted device-by-device to achieve essentially the same junction temperature at each device.

Abstract: A method and system for establishing a wireless connection between a portable computer system and a wireless network, particularly when the portable computer system goes out of coverage and a wireless connection needs to be re-established. The portable computer system has a main processor and a digital signal processor (DSP). The main processor is placed in a low power mode, conserving battery power. When the portable computer system goes out of coverage, broadcast channels used by the wireless network are scanned by the DSP instead of the main processor to identify channels that have sufficient signal strength for the wireless connection. Thus, the main processor remains in the low power mode. When the DSP identifies acceptable channels, it wakes up the main processor and identifies the channels having sufficient signal strength. The main processor then establishes a wireless connection using one of the channels identified by the DSP.

Abstract: Systems and methods for reducing temperature dissipation during burn-in testing are described. A plurality of devices under test are each subject to a body bias voltage. The body bias voltage is selected to substantially minimize leakage current associated with the plurality of devices under test. Accordingly, heat dissipation is reduced during burn-in.

Abstract: The present invention is a system and method of facilitating automatic generation of the source code in a convenient and efficient manner. In one embodiment of the present invention, a programmable system on a chip (PSoC) boot file generation method is utilized to create a boot file. A boot template file is created comprising special symbolic variable names that point to configuration registers within a programmable system on a chip (PSoC). User module selections are received with delineation of preferred configurations and functions associated with components of said programmable system on a chip (PSoC). Application files are automatically generated based upon user selections of PSoC configurations and functions. The special symbolic variable names are substituted or replaced with actual configuration register names. In one embodiment, a present invention programmable system on a chip (PSOC) boot file generation method also facilitates providing interrupt processing routines to the appropriate vector.

Abstract: An integrated circuit package is disclosed. The integrated circuit package includes a package substrate having a top and a bottom. Further, the integrated circuit package includes a plurality of bypass capacitors coupled to the bottom of the package substrate without a cavity. Moreover, the integrated circuit package includes an array of solder balls formed on the bottom of the package substrate. The array of solder balls facilitates surface mounting to a printed circuit board assembly. Also, the solder balls provide sufficient space between the printed circuit board assembly and the bypass capacitors. In an embodiment, the package substrate is an organic substrate.

Abstract: Embodiments of the present invention relate to a switched-capacitor filter which comprises a first stage which itself comprises a first switched capacitor, a second stage which itself comprises a second switched capacitor, a switched capacitive element that couples the output of the first stage to the input of the second stage, and a non-switched capacitive element coupled from the output of the second stage to the input of the first stage to provide damping of the switched-capacitor filter. Both stages are implemented as inverting analog amplifiers and the filter is especially well suited to semiconductor manufacture. The switched capacitor filter is implemented as part of a user module in a programmable system on a chip, or PSoC.

Abstract: A method for applying instructions to a microprocessor during test mode is disclosed. In one embodiment of the present invention, first a test mode is entered, establishing the microprocessor as a slave and a test controller as a master. Then, the test controller fills an instruction queue with instructions to be executed. The instructions originate from a test interface. A memory, such as a program flash, coupled to the microprocessor is bypassed; thus, the microprocessor is forced to execute instructions from the instruction queue. In another embodiment, the test controller transfers to the instruction queue an instruction to be executed in the microprocessor. Then, the instruction causes instructions from a supervisory memory to be executed by the microprocessor. The supervisory memory comprises pre-determined test instructions.

Abstract: A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its power requirements to the power supply pump circuit and in response, the power supply pump circuit controls the operating voltage with optimal efficiency. The dynamic update of power supply pump circuit results in an efficient use of the power supply pump circuit and thus results in a reduction of the number of dry cell batteries to only a single cell. Incorporation of the microcontroller and power supply pump circuit onto a single chip reduces the pin number requirements as well as the space required on the printed circuit board.