Patents Represented by Attorney Myers Bigel, et al.
  • Patent number: 8283256
    Abstract: Methods of forming substrates having two-sided microstructures therein include selectively etching a first surface of the substrate to define a plurality of alignment keys therein that extend through the substrate to a second surface thereof. A direct photolithographic alignment step is then performed on a second surface of the substrate by aligning a photolithography mask to the plurality of alignment keys at the second surface. This direct alignment step is performed during steps to photolithographically define patterns in the second surface.
    Type: Grant
    Filed: February 24, 2011
    Date of Patent: October 9, 2012
    Assignee: Integrated Device Technology inc.
    Inventors: Wanling Pan, Harmeet Bhugra
  • Patent number: 8160272
    Abstract: An audio output circuit includes a port attenuation circuit, which is configured to convert an abrupt dc voltage offset transition between a pair of audio signals received in sequence at an input thereof into a more gradual transition. This conversion is achieved by performing, in sequence, a ramp-to-mute operation on a first of the pair of audio signals and a ramp-from-mute operation on a second of the pair of audio signals. The ramp-to-mute operation includes ramping an output of the audio output circuit from a dc voltage offset associated with the first of the pair of audio signals to a reference dc voltage offset. The ramp-from-mute operation includes ramping the output of the audio output circuit from the reference dc voltage offset to a dc voltage offset associated with the second of the pair of audio signals. These ramping operations may be performed using voltage steps having uniform step size.
    Type: Grant
    Filed: July 15, 2008
    Date of Patent: April 17, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Jeffrey Blackburn, Ajaykumar Kanji
  • Patent number: 8134414
    Abstract: Exemplary embodiments provide a reference signal generator having a reference or center frequency within a predetermined variance over variations in temperature within a specified range. An exemplary apparatus comprises a reference resonator to generate a first reference signal having a resonant frequency, with the reference resonator having a first temperature dependence; and a plurality of switchable circuits, with at least one switchable circuit providing a second temperature dependence opposing the first temperature dependence to maintain the resonant frequency within a predetermined variance over a temperature variation.
    Type: Grant
    Filed: April 23, 2010
    Date of Patent: March 13, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Michael Shannon McCorquodale, Scott Michael Pernia, Vidyabhusan Gupta, Nathaniel Charles Gaskin, Nader Fayyaz
  • Patent number: 8106724
    Abstract: Micro-electromechanical acoustic resonators include a substrate having a cavity therein and a resonator body suspended over the cavity. The resonator body is anchored on opposing sides thereof (by support beams) to first and second portions of the substrate. These first and second portions of the substrate, which extend over the cavity as first and second ledges, respectively, each have at least one perforation therein disposed over the cavity. These perforations may be open or filled. The first and second ledges are formed of a first material (e.g., silicon) and the first and second ledges are filled with a second material having a relatively high acoustic impedance relative to the first material. This second material may include a material selected from a group consisting of tungsten (W), copper (Cu), molybdenum (Mo).
    Type: Grant
    Filed: July 23, 2009
    Date of Patent: January 31, 2012
    Assignee: Integrated Device Technologies, inc.
    Inventors: Ye Wang, Seungbae Lee, Harmeet Bhugra
  • Patent number: 8093958
    Abstract: Exemplary embodiments of the invention provide a reference signal generator having a controlled quality (“Q”) factor. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, which generates a first reference signal having a resonant frequency, and a plurality of reactance modules couplable to the reference resonator. Each reactance module comprises one or more reactance unit cells, and each reactance unit cell comprises a reactance element coupled in series to a switching element. In exemplary embodiments, the reactance element is a capacitor having a predetermined unit of capacitance, and the switching element is a transistor having a predetermined resistance when in an off state. The ratio of capacitance to resistance is substantially constant for all reactance modules of the plurality of reactance modules.
    Type: Grant
    Filed: January 12, 2008
    Date of Patent: January 10, 2012
    Assignee: Integrated Device Technology, Inc.
    Inventors: Justin O'Day, Michael Shannon McCorquodale, Scott Michael Pernia, Nam Duc Nguyen, Ralph Beaudouin, Sundus Kubba
  • Patent number: 8095813
    Abstract: Exemplary embodiments of the invention provide a clock generation apparatus, system, and method, which include power management. The apparatus is couplable to second circuitry which has a clock input terminal and an inverted clock output terminal. An exemplary apparatus comprises a clock generator, a sensor, and a processor. The clock generator provides a clock signal on a first terminal which is couplable to the clock input terminal of the second circuitry. The sensor is coupled to a second terminal which is couplable to the inverted clock output terminal, and detects a power conservation mode and a power resumption mode of the second circuitry. The processor is adapted to reduce power to the clock generator and to provide a first predetermined voltage or a second predetermined voltage to the first and second terminals in response to the detection of the power conservation mode, and to increase power to the clock generator in response to the detection of the power resumption mode.
    Type: Grant
    Filed: December 30, 2007
    Date of Patent: January 10, 2012
    Assignee: Integrated Device Technology, inc
    Inventors: Scott Michael Pernia, Tunc Mahmut Cenger
  • Patent number: 8072259
    Abstract: N-channel field effect transistor Proportional To Absolute Temperature (N-PTAT) cells are connected to a first supply voltage and P-channel field effect transistor Proportional To Absolute Temperature (P-PTAT) cells are connected to a second supply voltage. A coupling circuit connects at least one of the N-PTAT cells to at least one of the P-PTAT cells. These circuits can be used to provide a voltage reference and/or a supply voltage level detector. Related operating methods are also described.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: December 6, 2011
    Assignee: Integrated Device Technology, inc.
    Inventor: Tacettin Isik
  • Patent number: 8023594
    Abstract: A biphase mark signal receiver includes a data and clock recovery circuit. The data recovery circuit may include a coarse recovery stage and a fine recovery stage. The coarse recovery stage is configured to detect repeating occurrences of a first preamble (e.g., Y-preamble) within a biphase encoded data stream received by the data recovery circuit. The fine recovery stage is configured to generate a recovered data stream, in response to estimating a plurality of timing decision points (e.g., 3UI, 2UI and 1UI) from the repeating occurrences of the first preamble detected by the coarse recovery stage.
    Type: Grant
    Filed: July 11, 2008
    Date of Patent: September 20, 2011
    Assignee: Integrated Device Technology, inc.
    Inventors: Qi Li, Xiaoqian Zhang, Zhiyong Guan
  • Patent number: 7990226
    Abstract: A load circuit for a crystal oscillator includes a plurality of capacitors and a load control circuit configured to selectively add the capacitors to a load at a terminal of the crystal oscillator responsive to a command signal to provide a non-linear capacitive load at the terminal of the crystal oscillator that compensates for a non-linearity of a frequency versus load capacitance characteristic of the crystal oscillator. The load circuit may include a plurality of switches, respective ones of which are configured to load a terminal of the crystal oscillator with respective ones of the capacitors, and control circuit configured to control the plurality of switches to load the terminal of the crystal oscillator responsive to a binary command signal such that respective single ones of the switches operates in response to respective quantum changes a binary command signal over an operating range of the binary command signal.
    Type: Grant
    Filed: May 11, 2009
    Date of Patent: August 2, 2011
    Assignee: Integrated Device Technology, Inc.
    Inventor: Stephen E. Aycock
  • Patent number: 7978017
    Abstract: Exemplary embodiments of the invention provide a reference signal generator, system and method. An exemplary apparatus to generate a harmonic reference signal includes a reference resonator, such as an LC-tank, a control voltage generator adapted to provide a temperature-dependent control voltage; and a plurality of variable reactance modules. The reference resonator generates a first reference signal having a resonant frequency, and each reactance module is adapted to modify a corresponding reactance in response to the control voltage to maintain the resonant frequency substantially constant or within a predetermined variance over a predetermined temperature range. A frequency controller may also be included to maintain substantially constant a magnitude of a peak amplitude of the first reference signal and maintains substantially constant a common mode voltage level of the reference resonator.
    Type: Grant
    Filed: January 12, 2008
    Date of Patent: July 12, 2011
    Assignee: Integrated Device Technology, Inc.
    Inventors: Scott Michael Pernia, Nam Duc Nguyen, Michael Shannon McCorquodale, Justin O'Day, Ralph Beaudouin, Sundus Kubba
  • Patent number: 7955885
    Abstract: Methods of forming packaged micro-electromechanical devices include forming a first substrate having a micro-electromechanical device therein, which extends adjacent a first surface of the first substrate. A first surface of a second substrate is then bonded to the first surface of the first substrate, to thereby encapsulate the micro-electromechanical device within a space provided between the first and second substrates. Subsequent to bonding, a second surface of the second substrate is selectively etched to define at least one through-substrate opening therein, which exposes an electrode of the micro-electromechanical device. Thereafter, the through-substrate opening is filled with an electrically conductive through-substrate via.
    Type: Grant
    Filed: January 9, 2009
    Date of Patent: June 7, 2011
    Assignee: Integrated Device Technology, Inc.
    Inventors: Harmeet Bhugra, Kuolung Lei, Ye Wang
  • Patent number: 7939990
    Abstract: Micro-electromechanical acoustic resonators include a resonator body suspended over a substrate. The resonator body may have a single perforation therein, which may extend substantially or completely therethrough. The resonator body may also be configured to have a center-of-mass within an interior of the perforation and/or a nodal line that overlaps the perforation. A perimeter and depth of the single perforation can be configured to reduce a susceptibility of the acoustic resonator to process-induced variations in resonant frequency relative to an otherwise equivalent resonator that omits the single perforation. In other embodiments, the resonator body may have multiple perforations therein that extend along a nodal line of the resonator.
    Type: Grant
    Filed: February 26, 2009
    Date of Patent: May 10, 2011
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ye Wang, Harmeet Bhugra
  • Patent number: 7886176
    Abstract: Circuits for measuring a clock signal include a variable digital delay line that is configured to delay the clock signal by variable amounts in response to variable values of a digital control word that are applied thereto, to produce a variably delayed clock signal. A capture stage is responsive to the variably delayed clock signal and to the clock signal to capture a logic state of the variably delayed clock signal during transitions of the clock signal. A controller is configured to generate the variable values of the digital control word that are applied to the variable digital delay line and to identify a value of the digital control word in response to the capture stage capturing a change in the logic state of the variably delayed clock signal during a transition of the clock signal. Related methods and memory devices are also described.
    Type: Grant
    Filed: September 24, 2007
    Date of Patent: February 8, 2011
    Assignee: Integrated Device Technology, Inc.
    Inventor: Mikhail Svoiski
  • Patent number: 7882280
    Abstract: A packet switching integrated circuit chip is configured to receive packets, e.g., RapidIO™-compliant packets, from a plurality of external sources, and selectively passes data in the received packets to a plurality of external recipients. The chip is configured to pass first received packets without modification and to terminate second received packets and preprocess payloads thereof to produce new packets. The chip may be configured to perform signal sample processing operations on the second received packets, such as bit extension, bit truncation, bit reordering and/or bit arithmetic operations. The chip may be further configured to manage the first and second received packets based on destination addresses in the received packets.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: February 1, 2011
    Assignee: Integrated Device Technology, inc.
    Inventors: Bertan Tezcan, William Terry Beane, Scott Darnell
  • Patent number: 7871857
    Abstract: Methods of forming multi-chip semiconductor substrates include forming a first plurality of dicing streets in a first surface of a first semiconductor wafer having a first plurality of bonding sites thereon and forming a second plurality of dicing streets in a first surface of a second semiconductor wafer having a second plurality of bonding sites thereon. The first surfaces of the first and second semiconductor wafers are bonded together so that the first plurality of dicing streets are aligned with the second plurality of dicing streets and the first plurality of bonding sites are matingly received and permanently affixed within the second plurality of bonding sites. A plurality of bonded pairs of semiconductor chips are then formed by planarizing the second surface of the second semiconductor wafer until the second plurality of dicing streets are exposed.
    Type: Grant
    Filed: September 29, 2008
    Date of Patent: January 18, 2011
    Assignee: Integrated Device Technology, inc.
    Inventors: Kuolung Lei, Harmeet Bhugra
  • Patent number: 7872541
    Abstract: In various embodiments, the invention provides a clock generator and/or a timing and frequency reference comprising an LC oscillator with a frequency controller to control and provide a stable resonant frequency. Such stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the oscillator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: January 18, 2011
    Assignee: Mobius Microsystems, Inc.
    Inventors: Michael Shannon McCorquodale, Scott Michael Pernia, Sundus Kubba
  • Patent number: 7842613
    Abstract: Methods of forming a substrate for microelectronic packaging may include electroplating a metal seed layer onto a sidewall of a trench extending through the substrate. The sidewall may be patterned to have at least one slot therein that extends through the substrate. This slot is formed to be sufficiently narrow to block plating of the metal seed layer onto sidewalls of the slot. Thereafter, the at least a pair of electrodes are selectively electroplated onto side-by-side portions of the metal seed layer on the sidewall of the trench. During this electroplating step, the slot is used to provide a self-aligned separation between the pair of electrodes.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: November 30, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventor: Kuolung Lei
  • Patent number: 7834524
    Abstract: Micro-electromechanical devices include a temperature-compensation capacitor and a thin-film bulk acoustic resonator having a first terminal electrically coupled to an electrode of the temperature-compensation capacitor. The temperature-compensation capacitor includes a bimorph beam having a first electrode thereon and a second electrode extending opposite the first electrode. This bimorph beam is configured to yield an increase in spacing between the first and second electrodes in response to an increase in temperature of the micro-electromechanical device. This increase in spacing between the first and second electrodes leads to a decrease in capacitance of the temperature-compensation capacitor. Advantageously, this decrease in capacitance can be used to counteract a negative temperature coefficient of frequency associated with the thin-film bulk acoustic resonator, and thereby render the resonant frequency of the micro-electromechanical device more stable in response to temperature fluctuations.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: November 16, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Ye Wang, Harmeet Bhugra
  • Patent number: 7825777
    Abstract: An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n?1, . . . , 0]) and a second n-bit operand (e.g., B[n?1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( … ? ( ( C i ? ( A 0 + B 0 _ ) + A 0 ? B 0 _ ) ? ( A 1 + B 1 _ ) + A 1 ? B 1 _ ) ? … ? ( A n - 2 + B n - 2 _ ) + A n - 2 ? B n - 2 _ ) ? ( A n - 1 + B n - 1 _ ) + A n - 1 ? B n - 1 _ , “n” is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: November 2, 2010
    Assignee: Integrated Device Technology, Inc.
    Inventors: Tingjun Wen, David Walter Carr, Tadeusz Kwasniewski
  • Patent number: 7800282
    Abstract: Oscillators include a resonator having first and second electrodes and configured to resonate at a first frequency at which the first and second electrodes carry in-phase signals and at a second frequency at which the first and second electrodes carry out-of-phase signals. A driver circuit is configured to selectively sustain either the in-phase signals on the first and second electrodes or the out-of-phase signals on the first and second electrodes so that the resonator selectively resonates at either the first frequency or the second frequency, respectively. Related oscillator operating methods are also disclosed.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: September 21, 2010
    Assignee: Integrated Device Technology, inc.
    Inventors: Farrokh Ayazi, Reza Abdolvand, Seyed Hossein Miri Lavasani