Abstract: In various embodiments, the invention provides a frequency controller to control and provide a stable resonant frequency of a clock generator and/or a timing and frequency reference. Such stability is provided over variations in a selected parameter such as temperature and fabrication process variations. The various apparatus embodiments include a sensor adapted to provide a signal in response to at least one parameter of a plurality of parameters; and a frequency controller adapted to modify the resonant frequency in response to the second signal. In exemplary embodiments, the sensor is implemented as a current source responsive to temperature fluctuations, and the frequency controller is implemented as a plurality of controlled reactance modules which are selectively couplable to the resonator or to one or more control voltages. The controlled reactance modules may include fixed or variable capacitances or inductances, and may be binary weighted.

Abstract: Anti-pop circuits are provided for an audio amplifier that uses a power supply voltage and a ground voltage to drive a load with an audio signal that is centered about a virtual analog ground. These anti-pop circuits include a variable resistor and a capacitor that are connected to the audio amplifier to provide a low pass filter. The variable resistor has resistance that varies in response to a voltage level of the virtual analog ground, such as a difference between a voltage level of the power supply voltage and the voltage level of the virtual analog ground. The variable resistor may be a field effect transistor having a gate that is responsive to the differences between the voltage level of the power supply voltage and the voltage level of the virtual analog ground. The capacitor may be a field effect transistor, as well. Related methods are also described.

Abstract: An integrated circuit memory system includes a write-back buffer and a control circuit that support read-write-modify (RWM) operations within a high capacity memory device. A RWM operation may include reading from the integrated circuit memory device and the write-back buffer to identify whether the memory device or the write-back buffer has the data requested by a read instruction issued to the memory system. The data read from the write-back buffer is then written into the memory device and a modified version of the requested data is written to the write-back buffer in anticipation of subsequent transfer to the memory device.

Abstract: A packet processing integrated circuit chip includes a plurality of input ports configured to receive packets from respective external sources and a plurality of output ports configured to transmit packets to respective external recipients. The chip further includes a packet processor configurable to extract data from payloads of the received packets, to process the extracted data to produce new packets with payloads having formats compatible with data structures of the external recipients, and to convey the new packets to the output ports. The chip may further include a packet switching fabric configured to route selected packets from the input ports to selected ones of the output ports without payload modification.

Abstract: An integrated circuit comparator includes a pair of differential input transistors having gate terminals configured to receive a pair of differential input signals and a comparator output circuit electrically coupled to the pair of differential input transistors. A pair of differential offset compensation transistors are also provided. This pair of differential offset compensation transistors, which is electrically coupled to the pair of differential input transistors, has gate terminals that are configured to receive a pair of unequal dc offset voltages.