Abstract: A method of conducting a search using a mobile electronic device may include playing digital audio content at the mobile electronic device, and accepting user input at the mobile electronic device to capture a portion of the digital audio content. Search criteria may be provided wherein the search criteria is based on the captured portion of the digital audio content and on information separate from the captured portion of the digital audio content. A search may be conducted using the search criteria based on the captured portion of the digital audio content and on the information separate from the captured portion of the digital audio content. A result of the search may be provided at the mobile electronic device, and the result of the search may be displayed at the mobile electronic device.

Abstract: Numerous embodiments are provided that may be used to provide enhanced capacity and/or Quality-of-Service for OFDM-based systems such as LTE and/or WiMAX. Various service/device modes and/or applications are also provided. According to embodiments of the invention, a transformation may be performed on a data vector by a transmitter, prior to the transmitter transmitting the data vector, to distribute elements of the data vector over an available frequency space, thus providing robustness to channel anomalies such as fading and/or interference. The transformation may be based upon a Fourier transform or a truncated Butler matrix. At a receiver, an inverse of the transformation may be applied to recover data. The receiver and/or transmitter may be configured with an antenna array that may comprise a two-dimensional lattice of antenna elements, and may further be configured to estimate a number of resolvable signal paths and to form a spatial filter/rake that is matched to the number of resolvable signal paths.

Abstract: In a method of designing a mask layout, a wiring region for forming a metal wire is established, the wiring region having at least a standard width. Contact regions for forming contacts electrically connected to the metal wire are established in the wiring region. The contact regions adjacent to each other are grouped to divide the wiring region into a first region and a second region including the contact regions. First dummy regions are established in the first region, the first dummy regions corresponding to regions for forming first dummy patterns. Second dummy regions are established among the contact regions in the second region, the second dummy regions corresponding to regions for forming second dummy patterns.

Abstract: The present invention relates to a device adapted in order to decrease stress on connection points between a heat generating source and a substrate. The device 13 comprises a larger heat-dissipating part 7, and at least one smaller heat-dissipating part 6. The larger part 7 is arranged with at least one cavity 8 for housing the at least one smaller part 6. The at least one smaller part 6 is adapted to be attached to at least one heat-generating source 2, and at the same time more mobile in the cavity 8 and/or less affected by changes in temperature than the larger part.

Abstract: Provided are methods for fabricating semiconductor devices. A method may include forming a device isolation layer to define active regions on a semiconductor substrate. The active regions may protrude above an upper surface of the device isolation layer. The method may also include forming tunnel insulating layers on upper and side surfaces of corresponding ones of the active regions. The method may further include forming charge storage patterns on corresponding ones of the tunnel insulating layers. The charge storage patterns may be separated from each other. The method may also include forming a blocking insulating layer on the charge storage patterns and the device isolation layer. The method may further include forming a gate electrode on the blocking insulating layer. The blocking insulating layer may cover the device isolation layer such that the gate electrode is precluded from contact with the device isolation layer and the tunnel insulating layers.

Abstract: Methods of forming integrated circuit devices include forming an interlayer insulating layer having a trench therein, on a substrate and forming an electrical interconnect (e.g., Cu damascene interconnect) in the trench. An upper surface of the interlayer insulating layer is recessed to expose sidewalls of the electrical interconnect. An electrically insulating first capping pattern is formed on the recessed upper surface of the interlayer insulating layer and on the exposed sidewalls of the electrical interconnect, but is removed from an upper surface of the electrical interconnect. A metal diffusion barrier layer is formed on an upper surface of the electrical interconnect, however, the first capping pattern is used to block formation of the metal diffusion barrier layer on the sidewalls of the electrical interconnect. This metal diffusion barrier layer may be formed using an electroless plating technique.

Abstract: An apparatus for generating a voltage required for a semiconductor device by using a voltage supplied from an external power supply is provided.

Abstract: An acoustic panel includes a main body portion having a substantially planar front surface for orientation toward a sound source and an opposite, substantially convoluted rear surface. An airflow-resistive layer of material is secured to the planar front surface in face-to-face contacting relationship. The airflow-resistive layer of material may have a specific airflow resistance of between about 50-20,000 mks rayls, and may be configured to attenuate sound at one or more predetermined frequencies. A depth of convolution of the rear surface is between about forty percent to about seventy-five percent (40%-75%) of a thickness of the main body portion.

Abstract: A UPS is operated by deasserting a static switch drive signal, e.g., a gate signal to a thyristor, and then delaying provision of power from a converter circuit of the UPS, e.g., an inverter or other source of AC power, until after the switch has current commutated to an off state. For example, expiration of a predetermined time interval following deassertion of the switch drive signal may be detected, and the converter circuit may be enabled to drive the output of the UPS responsive to the detected expiration of the predetermined time interval. Alternatively, a current in the static switch may be detected, and the converter circuit may be enabled to drive the output of the UPS responsive to the detected current. The invention may be embodied as methods and apparatus.

Abstract: Control of uplink transmit power for a first mobile station operating with scheduled uplink data transmissions. A change in uplink scheduled status for the first mobile station is detected (301). Filtering of uplink interference measurements for the first mobile station is adapted (302) to account for the detected change in uplink scheduled status for the first mobile station. Alternatively a change in uplink scheduled status for a second mobile station is detected and a current filtering state for filtering of uplink interference measurements for the first mobile station is adjusted by applying an estimated expected change in interference associated with the detected change. A signal quality for uplink transmissions from the first mobile station is determined (303) based on measurements of received signal strength from the mobile station and the filtered uplink interference measurements.

Abstract: A nonvolatile memory device may include a memory cell array having a plurality of nonvolatile memory cells arranged in a matrix including a plurality of rows of the nonvolatile memory cells. Each of a plurality of word lines may be coupled with nonvolatile memory cells of a respective row of the matrix. A row decoder may be coupled to the plurality of word lines with the row decoder being configured to disable at least one of the word lines using a row bias having a level that is adjusted responsive to changes in temperature. Such a nonvolatile memory device may operate with reduced standby currents.

Abstract: A NAND flash memory device includes a control circuit configured to apply, during a program operation, a first word line voltage to non-selected ones of a plurality of serially-connected memory cells, a second word line voltage greater than the first word line voltage to a selected one of the plurality of memory cells, and a third word line voltage lower than the first word line voltage to a dummy memory cell connected in series with the plurality of memory cells. In other embodiments, a control circuit is configured to program a dummy memory cell before and/or after each erase operation on a plurality of memory cells connected in series therewith. In still other embodiments, a control circuit is configured to forego erasure of a dummy memory cell while erasing a plurality of memory cells connected in series therewith.

Abstract: An apparatus and method for quickly drying porous materials. A sealable chamber is connected to a cold trap which is connected to a vacuum pump. A sample is placed inside the sealable chamber. The vacuum pump is turned on and air is evacuated through the cold trap to the vacuum pump. Because evaporation may lower the temperature inside the sealable chamber, an infrared lamp may be used to heat the chamber and sample therein directly or heated air may be allowed to enter the sealable chamber in response to the vacuum created by the vacuum pump. Air may be drawn directly from the sealable chamber to the vacuum pump bypassing the cold trap. A load cell may be placed in the bottom of the sealable chamber to monitor the weight of a sample to determine if the drying process is complete. Other parameters could be used, including the degree of vacuum achieved in the chamber.

Abstract: A method of manufacturing a CMOS transistor can be provided by forming first and second gate electrodes on a substrate and forming a gate insulation layer on the first and second gate electrodes. A semiconductor channel material having a first conductivity type can be formed on the gate insulation layer. A pair of ohmic contacts can be formed on the semiconductor channel material such that the ohmic contacts cross over both side portions of the first gate electrode, respectively. A pair of Schottky contacts can be formed on the semiconductor channel material such that the Schottky contacts cross over both side portions of the second gate electrode, respectively.

Abstract: A semiconductor device includes a semiconductor substrate comprising a cell region and a peripheral circuit region, a first resistance layer and a second resistance layer spaced apart from each other and sequentially stacked on the semiconductor substrate of the peripheral circuit region, a first plug connected to the first resistance layer, and a second plug connected to the first and second resistance layers in common.

Abstract: Novel estrogenic compounds of Formula I are provided. wherein the bond represented by the wavy line may be a single or double bond such that when the wavy line is a single bond, R1 is selected from the group consisting of hydrogen, sulfate and glucoronate or other esters, and when the wavy line is a double bond, R1 does not exist; R2 is lower alkyl; R3 may be selected from the group consisting of hydrogen, sulfate, or glucuronide or other esters; and R4 through R13 may independently be selected from the group consisting of hydrogen, hydroxy, ketone, lower alkyl, lower alkoxy, halogen, and carbonyl groups and R14 is selected from the group consisting of hydrogen, sulfate and glucoronide and other esters. When R1 is hydroxy, the hydroxy or ester substituent may have either an ? or a ? orientation. Compositions of matter including compounds of the present invention are also provided as are methods of treating mammals in need of treatment using compounds of the present invention.

Abstract: A light emitting diode is provided having a Group III nitride based superlattice and a Group III nitride based active region on the superlattice. The active region has at least one quantum well stricture. The quantum well structure includes a first Group III nitride based barrier layer, a Group III nitride based quantum well layer on the first barrier layer and a second Group III nitride based barrier layer. A Group III nitride based semiconductor device and methods of fabricating a Group III nitride based semiconductor device having an active region comprising at least one quantum well structure are provided. The quantum well structure includes a well support layer comprising a Group III nitride, a quantum well layer comprising a Group III nitride on the well support layer and a cap layer comprising a Group III nitride on the quantum well layer.

Abstract: Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.

Abstract: Network element (400, 500), method and computer program for communication in a wireless communication network comprising: receiving at least one measured parameter value indicative of the channel quality on a radio channel at the processing unit (420, 520) of the network element (400, 500), calculating a deviation from a nominal parameter value indicative of the expected quality of the radio channel in the processing unit (420, 520), comparing the deviation from the nominal parameter value with at least a lower threshold value indicative of the lower threshold for the deviation from the nominal parameter value and/or an upper threshold value indicative of the upper threshold of deviation from the nominal parameter value and altering the gating scheme for the power control channel in the processing unit (420, 520) and using a control unit (450, 540) in the network element (400, 500) to signal the change of the gating scheme on control channel via the transceiver (410, 510).