Abstract: A probe card assembly can comprise an interface, which can be configured to receive from a tester test signals for testing an electronic device. The probe card assembly can further comprise probes for contacting the electronic device and electronic driver circuits for driving the test signals to ones of the probes.

Abstract: A method of forming an interconnection, including a spring contact element, by lithographic techniques. In one embodiment, the method includes applying a masking material over a first portion of a substrate, the masking material having an opening which will define a first portion of a spring structure, depositing a structure material (e.g., conductive material) in the opening, and overfilling the opening with the structure material, removing a portion of the structure material, and removing a first portion of the masking material. In this embodiment, at least a portion of the first portion of the spring structure is freed of masking material. In one aspect of the invention, the method includes planarizing the masking material layer and structure material to remove a portion of the structure material. In another aspect, the spring structure formed includes one of a post portion, a beam portion, and a tip structure portion.

Abstract: One embodiment of the present invention concerns a test assembly for testing product circuitry of a product die. In one embodiment, the test assembly includes at test die and an interconnection substrate for electrically coupling the test die to a host controller that communicates with the test die. The test die may be designed according to a design methodology that includes the step of concurrently designing test circuitry and a product circuitry in a unified design. The test circuitry can be designed to provide a high degree of fault coverage for the corresponding product circuitry generally without regard to the amount of silicon area that will be required by the test circuitry. The design methodology then partitions the unified design into the test die and the product die. The test die includes the test circuitry and the product die includes the product circuitry. The product and test die may then be fabricated on separate semiconductor wafers.

Abstract: An interconnection element of a spring (body) including a first resilient element with a first contact region and a second contact region and a first securing region and a second resilient element, with a third contact region and a second securing region. The second resilient element is coupled to the first resilient element through respective securing regions and positioned such that upon sufficient displacement of the first contact region toward the second resilient element, the second contact region will contact the third contact region. The interconnection, in one aspect, is of a size suitable for directly contacting a semiconductor device. A large substrate with a plurality of such interconnection elements can be used as a wafer-level contactor. The interconnection element, in another aspect, is of a size suitable for contacting a packaged semiconductor device, such as in an LGA package.

Abstract: In an integrated circuit assembly, know good die (KGD) are assembled on a substrate. Interconnect elements electrically connect pads on a die attached to the substrate to traces or other electrical conductors on the substrate or to pads on another die attached to the substrate. The substrate may have one or more openings, exposing pads of the die. The assembly may comprise one or more dice.

Abstract: A method and apparatus for testing a set of electronic devices can comprise placing electronic devices into a test station. A plurality of testers can provide test data to the test station. The test station can test the electronic devices using test data received from the plurality of testers. One of the testers can communication with another of the testers regarding the testing of the electronic devices. Probes can be used to contact the electronic devices, and one of the electronic devices can be contacted by more than one of the probes.

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract: Probe tips, methods for making probe tips, and method for using such probe trips are described. The probe tips can include a pedestal portion connected to a beam of a cantilever structure and a contact portion that can contact an electronic component that to be tested. The pedestal portion and contact portions can have a generally trapezoidal shape. The probe tips can also include a rectangular-shaped extension portion located between the base and contact portions. The probe tips can be made using a dual-etching process that creates the generally trapezoidal shape of the base and contact portions and the generally rectangular-shaped extension portion.

Abstract: Improved lithographic type microelectronic spring structures and methods are disclosed, for providing improved tip height over a substrate, an improved elastic range, increased strength and reliability, and increased spring rates. The improved structures are suitable for being formed from a single integrated layer (or series of layers) deposited over a molded sacrificial substrate, thus avoiding multiple stepped lithographic layers and reducing manufacturing costs. In particular, lithographic structures that are contoured in the z-direction are disclosed, for achieving the foregoing improvements. For example, structures having a U-shaped cross-section, a V-shaped cross-section, and/or one or more ribs running along a length of the spring are disclosed. The present invention additionally provides a lithographic type spring contact that is corrugated to increase its effective length and elastic range and to reduce its footprint over a substrate, and springs which are contoured in plan view.

Abstract: Bandwidth of a test channel is determined from a single port Time Domain Reflectometer (TDR) measurement with the channel terminated in a short or an open circuit. Bandwidth is estimated by: (1) making a TDR measurement of a channel terminated in a short or open circuit; (2) determining a maximum slope of the reflection from the TDR measurement; (3) calculating an interpolated rise or fall time, for example by taking 80% of the applied voltage between the 10% and 90% points, and then dividing the applied voltage by the maximum slope determined; (4) dividing the overall interpolated rise time by the square root of two to account for the TDR signal proceeding through the channel twice; (5) removing the contribution of rise time from measurement equipment; and (6) completing calculation of channel bandwidth using a formula to relate bandwidth to rise time, such as: bandwidth=0.35/rise time.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: A probe card assembly can include an insert holder configured to hold a probe insert, which can include probes disposed in a particular configuration for probing a device to be tested. The probe card assembly can provide an electrical interface to a tester that can control testing of the device, and while attached to the probe card assembly, the insert holder can hold the probe insert such that the probe insert is electrically connected to electrical paths within the probe card assembly that are part of the interface to the tester. The insert holder can be detached from the probe card assembly. The probe insert of the probe card assembly can be replaced by detaching the insert holder, replacing the probe insert with a new probe insert, and then reattaching the insert holder to the probe card assembly. The probe insert and holder can be integrally formed and comprise a single structure that can be detached from a probe card assembly and replaced with a different probe insert and holder.

Abstract: According to some embodiments, a method of determining a resistance of probes on a contactor device is disclosed. The contactor device can include a plurality of probes disposed to contact an electronic device to be tested. The method can include electrically connecting a pair of the probes to each other, and then forcing one of a voltage onto or a current through the pair of the probes. At a location on the contactor device, the other of a voltage across or a current through the pair of the probes can be sensed. A determination relating to a resistance of the probes can be determined from the values of the forced voltage or current and sensed other of the voltage or current.

Abstract: A method of forming a probe away includes forming a layer of tip material over a block of probe material. A first electric discharge machine (EDM) electrode is positioned over the layer of tip material, the EDM electrode having a plurality of openings corresponding to a plurality of probes to be formed. Excess material from the layer of tip material and the block of probe material is removed to form the plurality of probes. A substrate having a plurality of through holes corresponding to the plurality of probes is positioned so that the probes penetrate the plurality of through holes. The substrate is bonded to the plurality of probes. Excess probe material is removed so as to planarize the substrate.

Abstract: Resistances of signal paths within a interconnect structure for linking input/output (I/O) ports of an integrated circuit (IC) tester to test points of an IC are measured by the IC tester itself. To do so the interconnect structure is used to link the tester's I/O ports to a similar arrangement of test points linked to one another through conductors. Drivers within the tester, which normally transmit digital test signals to IC test points via the I/O ports when the IC is under test, are modified so that they may also either transmit a constant current through the I/O ports or link the I/O ports to ground or other reference potential. The tester then transmits known currents though the signal paths interconnecting the tester's I/O ports.

Abstract: Methods and apparatuses for testing semiconductor devices are disclosed. Over travel stops limit over travel of a device to be tested with respect to probes of a probe card assembly. Feedback control techniques are employed to control relative movement of the device and the probe card assembly. A probe card assembly includes flexible base for absorbing excessive over travel of the device to be tested with respect to the probe card assembly.

Abstract: Methods are provided for making plated through holes usable for inserting and attaching connector probes. In a first method, a curved plated through hole is formed by bonding curved etchable wires to a first substrate, plating the wires with a non-etchable conductive material, encasing the plated wires with a dielectric material to form a second substrate, planing the second substrate to expose the etchable wire, and etching the wires to leave plated through holes. In a second method, wires coated with a first etchable layer are initially bonded to a substrate, a second non-etchable plating layer is then applied over the first layer, and the first layer is etched away leaving plated through holes with wires disposed inside.

Abstract: A probe card assembly comprises multiple probe substrates attached to a mounting assembly. Each probe substrate includes a set of probes, and together, the sets of probes on each probe substrate compose an array of probes for contacting a device to be tested. Adjustment mechanisms are configured to impart forces to each probe substrate to move individually each substrate with respect to the mounting assembly. The adjustment mechanisms may translate each probe substrate in an “x,” “y,” and/or “z” direction and may further rotate each probe substrate about any one or more of the forgoing directions. The adjustment mechanisms may further change a shape of one or more of the probe substrates. The probes can thus be aligned and/or planarized with respect to contacts on the device to be tested.

Abstract: An interface device receives test data from a tester. A signal representing the test data is transmitted to a device under test through electromagnetically coupled structures on the interface device and the device under test. The device under test processes the test data and generates response data. A signal representing the response data is transmitted to the interface device through electromagnetically coupled structures on the device under test and the interface device.

Abstract: An electronic device is moved into a first position such that terminals of the electronic device are adjacent probes for making electrical contact with the terminals. The electronic device is then moved horizontally or diagonally such that the terminals contact the probes. Test data are then communicated to and from the electronic device through the probes.