Abstract: An improved single error correction circuit for a system memory storing in each of its addressable locations a data word and a corresponding error correcting code, which when read out from memory are fed to a syndrome generator which generates in output an error syndrome indication, comprising a set of registers arranged in banks, a first register in each bank for storing a prefixed portion of the data word read out from memory, the other registers in each bank for storing all the possible data configuration obtained from the prefixed portion of the data word stored in the first register of the same bank by inverting one data bit, so that a corrected read out data word is available in such registers in advance of syndrome indication which decoded, provides selection signal enabling one selected register per each bank to output, with minimum delay the latched portion of the data word.
Abstract: A digital timing unit for timing a data processing system or units thereof, wherein the output signals of a shift register are applied to a plurality of EXCLUSIVE OR gates (G.sub.1) . . . (G.sub.n). The shift register is activated from a known state so that an electric transition signal is shifted through the register cells. A timing cycle is thus defined which is utilized to set the register in a second known state. Feedback and control logic are provided for activating the register independently of its state and keeping it in the state occurring at the end of a timing cycle until a new start signal is received. Shifting of the register is caused by timing pulses generated by an oscillator (1). The timing signals generated by the timing unit and present on the output terminals of the EXCLUSIVE OR may be modified, as to the length, by changing the oscillator period and/or the connection between the EXCLUSIVE OR inputs and the outputs of the shift register.
Abstract: A minicomputer system is disclosed having a megabus with a plurality of processors and/or subprocessors, input/output (I/O) units and including logic for enabling the detection, decoding, storage and dispatching of data and instructions between the megabus and associated processors. The logic detects information addressed to its associated processors and synchronizes the transfers between the independently timed asynchronous processors and the units attached to the megabus.
Abstract: Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A reserved memory area associated with the currently active operating system is then addressed and register contents of a central processing unit are stored in the reserved memory area. The reserved memory of the operating system being activated is addressed and causes the address of the reserved memory of the operating system being activated, the data related to permitting the physical memory associated with the operating system being activated, contents of registers safestored in the reserve-memory and, data establishing the decor of the operating system being activated are entered in the central processing unit. The operating system to be activated is then enabled, and execution of permitted instructions by the second operating system is begun.
October 14, 1982
Date of Patent:
January 8, 1985
Honeywell Information Systems Inc.
Phillip A. Angelle, Marion G. Porter, James L. King
Abstract: Apparatus for determination of direction using the curl-free magnetic vector potential field. The apparatus includes apparatus for generating a predominantly curl-free magnetic vector potential field with a predetermined vector field spatial orientation. The field receiving apparatus includes a detecting apparatus with observable properties that vary with magnitude and orientation of an applied curl-free magnetic vector potential field. The apparatus can specify a direction of the field generating apparatus. A periodically rotating vector field can specify a path toward the field generating apparatus. The curl-free magnetic vector potential field can be established in conducting and opaque materials which are not capable of transmitting normal electromagnetic radiation.
Abstract: This relates to an apparatus and method for providing an accurate data group to the instruction buffer of a data processing system.The data group is simultaneously applied to the instruction buffer and to the error correcting apparatus. After analysis of the data group in the error correcting apparatus, the operation in progress is aborted if an error has been detected and the error is not correctable. If correctable, the correct instruction data group is applied to the execution unit. If no error is detected in the data group, utilization of the data group proceeds uninterrupted.Two, three state busses are employed. The first, three-state data bus is used to transmit memory data to the error detection and correction (EDAC) circuitry and to the data output circuits and to transmit input data to the memory. The second three state data transmits data to the instruction buffer, to the EDAC circuitry and also transmits corrected data from the data output circuits to the instruction buffer.
Abstract: In a data processing unit, apparatus permits more than one central processing unit and associated control interface unit to transfer data to an input/output multiplexer. Thus, more than one central processing unit can have access to a peripheral subsystem. Apparatus is provided which causes the input/output multiplexer to receive sets of data signal groups from the control interface units in sequential order. A signal-free period null signal period is provided by the control unit interface between each set of data signal groups (e.g., each data signal group set includes a single processor sequence). The signal-free period allows the input/output multiplexer to accept waiting data signals from the next sequential control interface unit. Once begun, the transfer of the entire set of data signal groups will proceed without interruption.
Abstract: An apparatus and method for encoding information receiving a binary information stream. The apparatus actuates one of four outputs as determined by the last output actuated and the binary level of the binary bit received.
Abstract: A clock pulse driver has applied to it a system clock pulse signal, or system clock and produces a first set of individually enabled clock pulse signals, the leading edges of the pulses of which substantially coincide with the leading edges of the pulses of the system clock, a second set and a third set of clock pulse signals, the trailing edges of the pulses of which substantially coincide with the leading edges of the pulses of the system clock. The width of the pulses of the three sets of output signals are controllable by first, second and third delay pulse signals. The clock pulse driver also produces delay signals the pulses of which have a predetermined relationship to the pulses of the system clock which delay signals can be used to control the widths of the first, second and third sets of clock signals produced by the driver circuits, and to control the delay or offset of the first, second and third sets of clock signals produced by the driver circuit.
Abstract: A solderable gold conductor composition is formed by dispersing gold and certain inorganic binders in an inert liquid vehicle composition which can be used to produce conductor patterns which patterns adhere to fired ceramic substrates and to which can be soldered leads of electronic components. Limited ranges in the composition of, and the amount of, the binder particularly the amount of copper oxide are effective to produce adhesion of the composition to fired substrates and in permitting copper leads of electronic devices to be soldered to pads of the gold composition using a lead-indium solder after the composition has been fired on a substrate. Strong solder joints are produced without the necessity for physically or chemically cleaning the pads prior to soldering. The binders comprise certain amounts of the crystalline materials, copper in the form of copper oxides CuO or Cu.sub.2 O, cadmium in the form of CdO, lead in the form of PbF.sub.
June 23, 1980
Date of Patent:
October 19, 1982
Honeywell Information Systems Inc.
Donald Neuhoff, Arthur H. Mones, Kit M. Lam
Abstract: In a computer system, with a system interface unit (SIU) for controlling data transfers between a lower speed main memory and either a central processor unit (CPU) or a high-speed cache memory unit (CMU), a cache memory command buffer (CMCB) circuit allows the SIU and CMU to operate independently of each other and ensures that commands to the CMU and SIU are executed in proper sequence. The CMCB circuit includes a stack sequence control scheme with circuitry for storing read and write signals from the CPU into read and write buffers and for outputting these signals to the CMU and SIU without interrupting the operation of either unit. The sequence control circuit includes an address decision network, a stack memory containing buffer pointers which indicate where the CPU read/write signals are located in the buffers, and a plurality of pointer registers or binary counters which indicate where buffer pointers (for particular read/write operations by the CMU or SIU) are located in the stack memory.
Abstract: An apparatus for receiving optically encoded binary data transmitted over an optical fiber from an optical transmitter device coupled to another data processing system. The receiver apparatus is used to convert the light signal carrying the subject data into TTL level digital logic signals. The receiver apparatus is comprised of circuitry for converting the optically encoded data into electrical signals in serial format, and circuitry for converting these electrical signals into TTL level digital signals in parallel format for use by a user device. The primary advantage of the apparatus disclosed here is the ability to substitute a single optical fiber for a plurality of parallel copper wires for carrying data between one data processing device and another with little or no loss in speed due to the larger bandwidth of optical fibers.
Abstract: Material handling apparatus in which a rectangular laminar fixture for a segment of film is provided with asymmetrically positioned recesses. The fixtures are adapted to be loaded into, stored in, and removed from a magazine provided with projections around which the recesses of the fixture stored in the magazine slidably fit. Only fixtures having the correct orientation with respect to the magazine can be stored within the magazine. The recesses of the fixtures and the projections of the magazine prevent a fixture stored in the magazine from changing its orientation.
Abstract: An information communication system having several transceivers connected to a communication medium. Each transceiver connected to a collision avoidance apparatus which determines if another transceiver is preparing to transmit on the communication medium by applying a unique predetermined D.C. voltage level to the communication medium.
Abstract: An apparatus and method correcting data groups within a data stream to form a corrected data stream and providing for selecting between the data stream and the corrected data stream as desired.
December 3, 1979
Date of Patent:
June 22, 1982
Honeywell Information Systems Inc.
Donn E. Bernhardt, Lowell D. McCulley, Jr.
Abstract: There is disclosed herein an apparatus for encoding, storing, updating and decoding data indicating the order of usage of memory locations as in a cache memory. An array of memory bits is encoded by a field programmable logic array each time a memory device or other peripheral is accessed by a method which need change only a portion of all the memory bits in a row. Each row corresponds to a group of memory locations or peripherals to be monitored. When the order of usage of a group of monitored locations is to be determined a field programmable logic array decodes the corresponding row and outputs a signal indicating the least recently used one of the memory locations of interest.
Abstract: Exposed surfaces of a layer of a copper thick film paste on a multilayer substrate are cleaned after being fired so that such surfaces are readily solderable to the extent that conventional tin/lead solders will wet said surfaces. The substrate with the exposed surfaces of a layer of a fired copper thick film paste is cleaned by being immersed in a warm dilute solution of an acid containing a fluoride ion, such as HF or HBF.sub.4 for a short period of time. After the short period of time of immersion has elapsed, the substrate is removed from the dilute acid solution and rinsed to remove substantially all traces of the cleaning solution.
Abstract: A control apparatus for a switching regulator circuit having a voltage controlled oscillator responsive to any deviation of the output voltage of the switching regulator circuit from a predetermined reference voltage. The voltage controlled oscillator produces a digital pulse stream having a frequency which is varied by the voltage controlled oscillator in response to any deviation of the output voltage of the switching regulator circuit from the predetermined reference voltage. A recovery detector is connected to at least one of the reactors of the switching regulator circuit to ensure that the particular SCR associated with that reactor has fully recovered prior to the next actuation thereof. If the particular SCR has not recovered then the digital pulse which would be distributed to that SCR within the digital pulse stream is held.
Abstract: An apparatus is disclosed herein for providing faster memory access for a CPU by utilizing a least recently used scheme for selecting a storage location in which to store data retrieved from main memory upon a cache miss. A duplicate directory arrangement is also disclosed for selective clearing of the cache in multiprocessor systems where data in a cache becomes obsolete by virtue of a change made to the corresponding data in main memory by another processor. The advantage of higher overall speed for CPU operations is achieved because of the higher hit ratio provided by the disclosed arrangement. In the preferred embodiment, the cache utilizes: a cache store for storing data; primary and duplicate directories for identifying the data stored in the cache; a full/empty array to mark the status of the storage locations; a least recently used array to indicate where incoming data should be stored; and a control means to orchestrate all these elements.