Abstract: A parallel operation keyboard (POK) which enables a user to provide multiple inputs simultaneously in managing a process control plant. A lock is provided to disable such simultaneous inputs. In an embodiment, multiple groups of keys are provided, with each group of keys being operable independently to modify the parameter value of a corresponding control loop. A network management station (NMS) and a server are designed to provide a suitable interface. In one implementation, each group of keys contains four keys respectively specifying increasing the parameter value, decreasing the parameter value, manual mode (in which the present level of the variable is controlled by the increase/decrease keys) and normal mode (in which the set point, i.e., the desired value, for the variable is controlled).

Abstract: Wireless field devices used in process control plants are configured over a wireless medium. In an embodiment, a host device discovers the presence of wireless field devices in the vicinity, and displays a list of discovered devices. The host device then enables a user to select a field device for configuration from the displayed list, and causes only the selected wireless field device to generate a human perceivable signal, thereby enabling a user to correlate a wireless field device listed in the display with the actual physical field device present in the vicinity. Upon confirmation from the user that the selected wireless field device is the device intended for configuration, the host device transmits the corresponding configuration parameters over the wireless medium, thus configuring the device.

Abstract: A management system (managing field devices of a process control plan) provided according to an aspect of the present invention enables a user to view historical menus (i.e., the menus as displayed at desired prior time points). Such a feature is enabled in an embodiment by storing displayed tree structure as well as associated item values.

Abstract: A lamp in which a LED array is coupled to a transistor such that the same amount of current flows through both. The voltage level at the control (e.g., base) terminal of the transistor is controlled such that the current magnitude is reduced when the operating temperature rises. As a result, the heat generated from the junctions of the LEDs in the LED arrays is reduced, thereby compensating for the increase in the operating temperature.

Abstract: According to an aspect of the present invention, device descriptions specified using different device description (DD) specifications are converted (represented) into a single format. In an embodiment, the single format corresponds to extended markup language (XML). The device description in the single format is then examined to provide a user interface for management of the corresponding field devices. Due to such use of a common format, integration of field devices (into a management system) having device description defined according to a new device description specification, may be simplified.

Abstract: Reestablishing connections when a block/device at one end is re-initialized. The data elements necessary for reestablishing a connection at both ends may be stored in a third device. When a block/device at one end is re-initialized, additional data elements necessary for reestablishing connection may be received from the re-initialized block, and all the data elements may be used to re-establish the connection. In an embodiment implemented in the context of a control system, a supervisory control station stores image of the various intermediate objects used in both end devices (at which ends of a connection terminate), receives parameters which identify changes when an end device is re-initialized, and makes changes to the stored intermediate objects. The changed objects are downloaded to the respective end devices to reestablish the connection.

Abstract: A multiplexer implemented substantially in the form of software, which enables the multiplexer to be integrated with a supervisory platform into one unit is disclosed. The multiplexer may contain a database which stores a mapping of the address of the devices to the corresponding port/channels to which the devices are connected. An emulation block implemented in software examines the address in each command/response and forwards the command/response appropriately. Due to the software implementation, some of the commands may be blocked (from being forwarded). According to another aspect, data required to generate a response may be retrieved from a controller block (instead of retrieving from the device), thereby reducing the overhead on the devices.

Abstract: A functional verification system suited for verifying the function of non-cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: Functional verification system enabling the state of difference signals to be traced. The signals represent the outputs resulting from the evaluation of combinatorial blocks and/or a plurality of state elements forming a target design. The combinatorial blocks and/or a plurality of state elements may be grouped into multiple clusters, with each cluster being identified by a cluster identifier. The tracing circuit may include a mask memory, a previous state memory, and trace controller. Each of the mask memory and the previous state memory may contain a number of locations equal to the number of clusters such that the relevant mask and previous state information may be accessed based on the cluster identifier. The trace controller receives evaluated outputs for a cluster at bit positions specified by a corresponding mask. The trace controller compares the received bits with the previous values, and generates an entry in a trace buffer to record any changes.

Abstract: A functional verification system suited for verifying the function of cycle based integrated circuits (IC) design. The IC design is divided into a plurality of combinatorial blocks connecting sequential elements. Truth tables corresponding to the divided blocks are computed and stored in a memory. The output values of the IC design are determined by evaluating the blocks. The evaluation typically entails one memory access as the truth tables are pre-computed and stored in a memory storage. Accordingly the output values are computed quickly. The storage is implemented using random access memories and a XCON is designed to ensure the dependencies are preserved during the evaluations.

Abstract: A run time controller which controls the sequence of evaluations of combinatorial blocks in a functional verification system. A target design is partitioned into multiple clusters, with each cluster in turn containing multiple combinatorial blocks. Evaluation units may be designed to evaluate the combinatorial blocks in each cluster in parallel. The run time controller may contain a flow processor, a flow control memory, and a cluster control memory. The contents of cluster control memory may be configured to specify how different condition bits/registers are to be altered upon evaluation of each cluster. The flow control memory is configured with instructions to data from different sources to be sent the evaluation units. In addition, the instructions are designed to examine the status of different registers and cause the flow processor to alter the evaluation flows.

Abstract: A graphics controller circuit for minimizing an amount of data received from a host. The graphics controller circuit includes a register file with a plurality of registers. The graphics controller accepts commands addressed to virtual registers, and generates plurality of instructions including an instruction to access one of the registers in the register file. By using such a virtual register number in a command and generating several instructions in response thereto, the graphics controller circuit of the present invention minimizes the amount of data host sends over the system bus.

Abstract: A functional verification system which can be used to evaluate either cycle based designs or non-cycle based designs. A target design is partitioned into multiple clusters, with a combinatorial block in each cluster being assigned to an evaluation unit. A flow control memory stores data indicating the sequence in which the clusters are to be evaluated. The evaluation units evaluate combinatorial blocks within a cluster in parallel. A cluster control memory indicates the manner in which a register is to be modified upon the evaluation (and results) of each cluster. The instructions in the flow control memory may be designed to examine the contents of the register and evaluate the clusters in different sequences depending on the content of the register. Evaluation of a loop of a non-cycle based design can thus be terminated based on the contents of the register.

Abstract: A functional verification system which provides information as to whether a signal has reached all possible states. For example, in the case of a signal with 0 and 1 as possible states, a 2 bit variable is initialized to 00. When a value of 1 is received for the signal, the first bit is set to 1 and when a value of 0 is received for the signal, the second bit is set to 1. Accordingly, by examining the two bits, one may determine whether the signal has attained one or both of 0 and 1 states.

Abstract: A flexible scheduler in an ATM switch. The scheduler enables each connection to be served fairly according to associated quality of service parameters, while enabling several other features. A connection can be shaped while minimizing additional memory and processing requirements. Specifically, the conformance time of cells of a connections need not be stored when significant backlog exists in the transmission of the cells. The shaping rate can be dynamically varied. Sequence of cells forming a frame are buffered in the ATM switch until the end of frame cell is received. All the cells of a frame are then sent in quick succession.

Abstract: A flexible scheduler in an ATM switch. The scheduler enables each connection to be served fairly according to associated quality of service parameters, while enabling several other features. A connection can be shaped while minimizing additional memory and processing requirements. Specifically, the conformance time of cells of a connections need not be stored when significant backlog exists in the transmission of the cells. The shaping rate can be dynamically varied. Sequence of cells forming a frame are buffered in the ATM switch until the end of frame cell is received. All the cells of a frame are then sent in quick succession.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

Abstract: A switch guaranteeing a minimum amount of memory space for desired connection while allowing efficient dynamic change of maximum memory space that can be used by a connection. Only an amount of memory space which is required for guaranteeing the minimum amount of memory space is reserved. When the reserved space is decremented due to new cells being received on connections, the maximum memory space reserved for each connection is dynamically increased. For multicast connections, only a single copy of the cell data is stored even though a multicast cell is transmitted on several ports. Multicast cells can also be processed using the same signals used for processing unicast cells.

Abstract: A receiver to recover data encoded at high speed in a signal over a serial communication channel. A static phase determination circuit indicates whether the signal is early, late or neutral relative to a sampling clock. The sampling clock is used to oversample the signal to generate multiple samples. A token analyzer examines the transitions around a current symbol to determine any short term phase shifts of the boundaries between symbols. The short term phase shifts and the static phase together may be used to accurately select the samples representing the symbols without requiring extensive processing.

Abstract: An automatic sampling control system for digital monitors. A clock generation circuit generates a sampling clock. A phase controller modifies the phase of the sampling clock by a phase amount. An ADC samples a frame of an analog display signal to generate digital samples. A value which is a function of the samples is generated. The function generally generates a larger value with correspondingly large sample values. The phase amount is modified for successive image frames until a maximum function value is generated. When successive image frames do not change substantially in image content, the phase amount represents the optimal phase change for the sampling clock. If the image content is changing substantially, the phase adjustment may be disabled.