Patents Represented by Attorney Neil B. Schulte
  • Patent number: 5241828
    Abstract: A Seebeck effect thermoelectric cooler, operative at cryogenic temperatures, in which two materials having different Seebeck coefficients are in electrical contact so that current flow thereacross cools the junction. One or both of the materials comprise a metal-insulator transition material characterized by doping, alloying, or other means to be just slightly metallic so that electrical resistance becomes lower at lower temperatures, but the Seebeck coefficient does not decline at lower temperatures, as would be the case if the material were allowed to become fully metal-like.
    Type: Grant
    Filed: July 17, 1992
    Date of Patent: September 7, 1993
    Assignee: Conductus, Inc.
    Inventor: Aharon Kapitulnik
  • Patent number: 4412238
    Abstract: In a monolithic semiconductor integrated circuit, conventional bipolar transistors are fabricated along with thin ion implanted junction field effect transistors, to create BIFET structures. After the conventional isolation diffusion, the surface oxide is stripped off and the semiconductor wafer ion implanted with slow diffusing impurities of a conductivity type, the same as the undiffused surface material. Then the bipolar transistors, along with the junction field effect transistors, are fabricated using conventional oxide masked diffusion processes. The field effect device sources and drains employ the base diffusions of the bipolar transistors while the gate contact is achieved with an emitter diffusion. The field effect device channels are formed at a depth substantially greater than that of the impurities deposited in the original ion implant. If desired, an ion implanted top gate can be established over the channel. The wafer is then annealed and processed in accordance with conventional techniques.
    Type: Grant
    Filed: May 27, 1980
    Date of Patent: October 25, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Wadie N. Khadder, Jia T. Wang, Brian E. Hollins
  • Patent number: 4405871
    Abstract: A CMOS integrated circuit power-on reset circuit has two cascaded threshold detectors for independently sensing the supply voltage attaining an amplitude sufficient to operate N and P-channel devices respectively and for providing a reset signal in response to the supply voltage meeting both conditions.
    Type: Grant
    Filed: May 1, 1980
    Date of Patent: September 20, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Gerald B. Buurma, John M. Jorgensen
  • Patent number: 4404660
    Abstract: A two-phase memory circuit provides for adjusting the precharge voltage of a data line to substantially equal the threshold voltage of a sense amplifier coupled to the data line during a first phase so that a relatively small voltage change on the data line during a second phase can be detected by the sense amplifier.
    Type: Grant
    Filed: May 23, 1980
    Date of Patent: September 13, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Abraham Menachem
  • Patent number: 4404673
    Abstract: An error correcting network adapted for encoding and decoding data transferred to and from a bubble memory has parallel linear encoder/decoder circuits. An error syndrome generated in response to a parity error in an initial read operation is used by one encoder/decoder circuit for correcting the parity error during a subsequent reread of the data. The error syndrome is also stored in a latch for comparison with a second error syndrome generated in response to the data during the reread operation. A true comparison between the two error syndromes verifies that that data has not changed between the two read operations due to a soft error and that the error correction of the first encoder/decoder circuit is valid.
    Type: Grant
    Filed: February 9, 1981
    Date of Patent: September 13, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Roy K. Yamanouchi
  • Patent number: 4397887
    Abstract: A process to program ROM's after the insulation, gates, and interconnect circuitry have been formed by using a contact mask to define openings at the depletion cells, which openings extend beside the gates to the sources and drain so as to allow phosphorus dopant to be diffused sideways under the gates to short out the cell.
    Type: Grant
    Filed: August 18, 1982
    Date of Patent: August 9, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Haluk M. Aytac, John F. MacDonald
  • Patent number: 4395774
    Abstract: Means are described for generating a pair of oscillator signals that will respectively drive P and N channel transistors in Class B. These signals are used to clock a synchronous inverter stage that will only change state during the appropriate time interval. Pairs of such stages are cascaded using common clocking to create a shift register which drives an output inverter, the output of which is coupled back to the input of the register. The output stage also has series-coupled P and N-channel transistor pairs for each pair of clocked inverters. Each transistor pair has its gates driven by the respective pair of clocked inverters. The output stage switches at a frequency which is a submultiple of the oscillator frequency, with the submultiple being equal to the number of inverters minus one. Since the inverters are fully Class B there is no direct current conduction due to simultaneous transistor conduction.
    Type: Grant
    Filed: January 12, 1981
    Date of Patent: July 26, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Adolph K. Rapp
  • Patent number: 4393575
    Abstract: A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One embodiment is a bipolar transistor including a collector region, a base region and an emitter region, the base region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a zener diode device with an anode region and a cathode region, the cathode region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a JFET with a gate region and a source and drain region and a channel region extending through the gate region between the source and drain regions, the channel region being provided with the shallow ion implanted layer at the surface thereof.
    Type: Grant
    Filed: July 20, 1981
    Date of Patent: July 19, 1983
    Assignee: National Semiconductor Corporation
    Inventors: James L. Dunkley, Robert C. Dobkin
  • Patent number: 4392935
    Abstract: An indexing system adapted to periodically advance a web of metal through a plating line that first advances gently till it engages a hole in the web, then closes clamping members about the web to grasp the web over a distributed region, and only then moves the web at full speed.
    Type: Grant
    Filed: September 29, 1982
    Date of Patent: July 12, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Syed A. Husain
  • Patent number: 4392016
    Abstract: In an AM stereo radio receiver a filter is coupled to the IF amplifier and is tuned to the IF carrier frequency. The filter will ring at the IF and, if desired, can be incorporated into an oscillator circuit. The resulting signal acts as a reinserted carrier that will persist over those intervals during which the carrier would ordinarily be absent due to amplitude overmodulation. In effect the oscillatory signal sets the minimum value to which the carrier can be driven and will act to prevent the noise bursts that ordinarily accompany excessive modulation. Such overmodulation can result from inadvertence at the transmitter or from multipath reception.
    Type: Grant
    Filed: March 2, 1981
    Date of Patent: July 5, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Don R. Sauer
  • Patent number: 4392150
    Abstract: A partial silicide layer under a polycrystalline silicon (polysi) first level interconnect reduces the sheet resistance of the first level interconnect. The polysi insulates the silicide from possibly reactive materials and gases. Since the silicide is not deposited over contacts between the polysi and the substrate, conventional polysi/silicon ohmic contacts can be made.
    Type: Grant
    Filed: October 27, 1980
    Date of Patent: July 5, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Francis G. Courreges
  • Patent number: 4390893
    Abstract: An interface circuit for converting a digital signal representing a dot-by-dot color video signal into a NTSC signal compatible with a television antenna input precompensates the digital for limitations in typical NTSC receivers. Various methods and circuits for precompensating the luminance amplitude, chrominance and chrominance amplitude content of the digital signal result in perceivably improved contrast and color purity.
    Type: Grant
    Filed: December 15, 1980
    Date of Patent: June 28, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Gilbert E. Russell, Hee Wong
  • Patent number: 4389296
    Abstract: A contact for making electrical connections to a moving strip of metal, so as to permit plating the strip, in which grooved members engage just the edges of the strip, thus avoiding scratches on the face of the strip.
    Type: Grant
    Filed: March 22, 1982
    Date of Patent: June 21, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Michael Seyffert, Steven W. Taatjes
  • Patent number: 4388699
    Abstract: A bubble sense amplifier has a biasing circuit for adjusting the bias currents through magneto-resistive detectors so as to establish a preferred common mode operating voltage across the bubble detectors. The preamplifier is coupled through a junction capacitance circuit to a clamp-and-strobe circuit and to a differential comparator. The differential comparator has a selectable threshold voltage, and compares the differential bubble signal to the selected threshold voltage.
    Type: Grant
    Filed: January 19, 1981
    Date of Patent: June 14, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Ramanatha V. Balakrishnan
  • Patent number: 4387349
    Abstract: A two transistor CMOS inverter has the two transistor gates coupled together by a coupling capacitor. D-C gate bias is supplied to each transistor through high value resistors. The P-channel transistor is biased one threshold below V.sub.DD and the N-channel transistor is biased one threshold above ground. The biasing voltages are developed through the use of a current mirror so that the biasing is independent of processing variables and temperature. This form of biasing renders the circuit class B regardless of the source to drain voltage and ensures low current operation. A crystal oscillator created using such an inverter and biasing will operate at voltages substantially below sum of P and N thresholds and at a current level about one-fifth of that of a conventional CMOS oscillator.
    Type: Grant
    Filed: December 15, 1980
    Date of Patent: June 7, 1983
    Assignee: National Semiconductor Corporation
    Inventor: A. Karl Rapp
  • Patent number: 4381460
    Abstract: A MOS two-phase boostrap driver circuit, having a bootstrap transistor with a gate selectively charged or discharged in response to the level of an input signal, provides for selectively charging the gate of the bootstrap transistor directly from a voltage supply.
    Type: Grant
    Filed: May 27, 1980
    Date of Patent: April 26, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Abraham Menachem
  • Patent number: 4379208
    Abstract: In an AM stereo radio receiver, a pilot signal is recovered from the phase modulated channel. The pilot signal is sensed by means of a bandpass filter tuned to the subaudible signal frequency and is used to operate a detector-switching amplifier combination. The switching amplifier actuates a visual indicator which shows the presence of a stereo broadcast. The receiver is provided with an electronic blend function that operates in response to the pilot signal and an excess phase signal that is present when the receiver is mistuned. OR Logic, which responds to either mistuning or a lack of stereo pilot signal, switches the receiver to monaural response. If desired, further OR Logic can include response to weak signals, in which case an improvement in signal to noise ratio is achieved.
    Type: Grant
    Filed: November 13, 1980
    Date of Patent: April 5, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Tim D. Isbell, Don R. Sauer
  • Patent number: 4378283
    Abstract: A consumable-anode selective plating apparatus for plating a continuous metal strip having a container for containing a consumable anode material, a mask assembly for exposing selected areas of said continuous metal strip to an electrolyte, a source of electrolyte and a source of power and conductors for passing a current through said electrolyte, consumable anode material and metal strip.
    Type: Grant
    Filed: July 30, 1981
    Date of Patent: March 29, 1983
    Assignee: National Semiconductor Corporation
    Inventors: Michael Seyffert, Gerald C. Laverty
  • Patent number: 4378529
    Abstract: A pair of common base connected transistors have their emitters coupled to provide the input terminals of a differential amplifier. The collectors are coupled to a current mirror that provides a small current bias that operates the transistors at equal current densities. The common bases are coupled to a node that is driven to a level that causes the bases to track the emitters with a one V.sub.BE offset that will therefore automatically adjust to conform to the applied current. When a remotely grounded transducer is coupled to the amplifier input it can operate at a common mode potential outside of the span of the power supply that operates the amplifier.
    Type: Grant
    Filed: September 8, 1981
    Date of Patent: March 29, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Robert C. Dobkin
  • Patent number: 4377855
    Abstract: A content-addressable memory (CAM) has an array of four-transistor memory cells arranged in rows corresponding to stored words and columns corresponding to a selected search word. Complementary column lines couple signals associated with the bits of the search word to the memory cells associated with all of the stored words in parallel. The memory cells of each row are coupled to a common sense line and cause a current to flow on the sense line in response to the search word not matching the data word associated with that row.Writing is accomplished by discharging one of the sense lines and applying signals representative of the desired word to be stored to the column lines. Since the ground lines are not unique to any row, they can be shared between adjacent rows or columns as best suits the layout of the circuit.A status bit is associated with each stored word and is used to selectively activate the sense amplifier associated with each row.
    Type: Grant
    Filed: November 6, 1980
    Date of Patent: March 22, 1983
    Assignee: National Semiconductor Corporation
    Inventor: Yoav Lavi